LF3347QC15 LODEV [LOGIC Devices Incorporated], LF3347QC15 Datasheet - Page 3

• Manufacturer Part Number: LF3347QC15
• Description: High-Speed Image Filter with Coefficient RAM
• Manufacturer: LODEV [LOGIC Devices Incorporated]

DEVICES INCORPORATED
OCEN — Output Clock Enable
When OCEN is LOW, the output
register is enabled for data loading.
When OCEN is HIGH, output register
loading is disabled and the register’s
contents will not change.
ACC — Accumulator Control
The ACC input determines whether
internal accumulation is performed. If
ACC is LOW, no accumulation is
performed, the prior accumulated sum
is cleared, and the current sum of
products is output. When ACC is
HIGH, the emerging product is added
to the sum of the previous products.
LD — Load Control
LD enables the loading of data into the
coefficient banks and control registers
(control registers are the round and limit
registers). When LD is LOW, data on
CC
rising edge of CCCLK. When LD is
HIGH, data cannot be loaded into the
coefficient banks and control registers.
When enabling the input circuitry for
data loading, the LF3347 requires a
HIGH to LOW transition of LD in order
to function properly. Therefore, LD
needs to be set HIGH immediately after
T
Register
RND15
LMT15
CS255
RND0
RND1
ABLE
11-0
LMT0
LMT1
CS0
CS1
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is latched into the device on the
2. R
Load Address
EGISTER
C00H
C01H
C0FH
0FFH
800H
801H
80FH
000H
001H
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F
ORMATS
31-16/15-0
31-16/15-0
31-16/15-0 Upper / Lower Limit Register 15
11-0
11-0
11-0
31-0
31-0
31-0
Bits
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power up to ensure proper operation of
the input circuitry.
It takes five CCCLK clock cycles to load
one coefficient set into the four coefficient
banks or to load one control register.
When the input circuitry is enabled (LD
goes LOW), the first value loaded into the
device on CC
determines what will be loaded (see
Table 2). The next four values loaded on
CC
coefficient banks or control register (see
Tables 3-5). After the last data value is
loaded, another coefficient bank address
or control register may be loaded by
feeding another address into CC
When all desired coefficient banks and
control registers are loaded, the input
circuitry must be disabled by setting LD HIGH.
SELRND
SELRND
which rounding register will be used
in the rounding circuit to round/offset
the data.
SHIFT
SHIFT
the 32-bits from the accumulator are
passed to the output (see Table 1).
11-0
Upper / Lower Limit Register 0
Upper / Lower Limit Register 0
4-0
4-0
is the data to be loaded into the
3-0
3-0
— Shift
determines which 16-bits of
Register Description
Rounding Register 15
High-Speed Image Filter with Coefficient RAM
Rounding Register 0
Rounding Register 1
Coefficient Set 255
— Round Select
allows the user to select
11-0
Coefficient Set 0
Coefficient Set 1
is an address which
3
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11-0
.
SELLMT
SELLMT
which limiting register will be used in
the limiting circuit to set the upper
and lower limits on the data.
LMTEN — Limit Enable
When LMTEN is LOW, limiting is
enabled and the selected limit register
is used to determine the valid range of
output values for the overall filter.
When HIGH, limiting is disabled.
F
A
FFH
IGURE
00H
01H
Video Imaging Products
7-0
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ULMT
LLMT
SHIFT
RND
3-0
3-0
31-0
15-0
15-0
4-0
2. R
— Limit Select
allows the user to control
SELRND
L
0 0 0 0
0 0 0 1
1 1 1 1
IMITING
OUNDING
32
32
32
SELECT
16
16
16
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LIMIT
RND
3-0
08/16/2000–LDS.3347-G
C
, S
IRCUITRY
SELLMT
LF3347
ELECTING
0 0 0 0
0 0 0 1
1 1 1 1
LMTEN
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3-0
,