LF3330QC15 LODEV [LOGIC Devices Incorporated], LF3330QC15 Datasheet - Page 3

• Manufacturer Part Number: LF3330QC15
• Description: Vertical Digital Image Filter
• Manufacturer: LODEV [LOGIC Devices Incorporated]

DEVICES INCORPORATED
SIGNAL DEFINITIONS
Power
V
+3.3 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers.
Inputs
DIN
DIN
input port. Data is latched on the rising
edge of CLK.
VB
VB
input port used only when implement-
ing Odd and Even Field Filtering (see
Functional Description section for a full
discussion). Data is latched on the
rising edge of CLK.
CF
CF
coefficient banks and configuration/
control registers. Data present on
CF
on the rising edge of CLK when LD is
LOW (see the LF Interface
a full discussion).
CA
CA
the coefficient banks is fed to the
multipliers. CA
Coefficient Address Register on the
rising edge of CLK when CEN is LOW.
Outputs
DOUT
DOUT
output port.
CC
11-0
11-0
11-0
11-0
11-0
7-0
7-0
11-0
11-0
and GND
— Coefficient Address
determines which row of data in
— Coefficient Input
is used to load data into the
is latched into the LF Interface
15-0
15-0
— Field Filtering Data Input
is the 12-bit registered data
— Data Input
is the 12-bit registered data
— Data Output
is the 16-bit registered data
7-0
is latched into the
TM
section for
TM
COUT
COUT
output port. COUT
device should be connected to
DIN
Controls
LD — Coefficient Load
When LD is LOW, data on CF
is latched into the LF Interface
on the rising edge of CLK. When
LD is HIGH, data can not be
latched into the LF Interface
When enabling the LF Interface
for data input, a HIGH to LOW
transition of LD is required in
order for the input circuitry to
function properly. Therefore, LD
must be set HIGH immediately
after power up to ensure proper
operation of the input circuitry
(see the LF Interface
a full discussion).
SLCT
F
T
00000
00001
00010
01110
01111
10000
IGURE
ABLE
·
·
·
11-0
(Sign)
–2
4-0
11-0
11-0
11 10 9
11
1. O
of another LF3330.
2. I
2
— Cascade Data Output
is a 12-bit cascade
10
S
F
F
F
F
F
F
·
·
·
15
16
17
29
30
31
15
Input Data
2
NPUT
UTPUT
9
S
F
F
F
F
F
F
·
·
·
3
14
14
15
16
28
29
30
F
11-0
TM
S
F
F
F
F
F
F
ORMATS
F
2
2
·
·
·
13
14
15
27
28
29
13
2
ORMATS
section for
on one
2
1
1
TM
· · ·
· · ·
· · ·
· · ·
· · ·
· · ·
· · ·
2
0
0
11-0
.
TM
TM
Vertical Digital Image Filter
PAUSE — LF Interface
When PAUSE is HIGH, the LF
Interface
until PAUSE is returned to a LOW
state. This effectively allows the user
to load coefficients and control
registers at a slower rate than the
master clock (see the LF Interface
section for a full discussion).
CEN — Coefficient Address Enable
When CEN is LOW, data on CA
latched into the Coefficient Address
Register on the rising edge of CLK.
When CEN is HIGH, data on CA
not latched and the register’s contents
will not be changed.
F
F
F
F
S
F
F
·
·
·
F
10
22
23
24
8
8
9
Video Imaging Products
IGURE
(Sign)
–2
(Sign)
11 10 9
F
F
F
–2
S
F
F
F
31 30 29
·
·
·
21
22
23
7
8
9
7
0
20
Accumulator Output
TM
2
3. A
Coefficient Data
2
–1
19
loading sequence is halted
2
· · ·
· · ·
· · ·
· · ·
· · ·
· · ·
· · ·
2
–2
CCUMULATOR
18
2
TM
2
2
–9
F
F
F
S
F
F
F
2
–9
11/08/2001–LDS.3330-M
·
·
·
16
17
18
2
2
3
4
Pause
2
2
1
–10
1
–10
LF3330
F
F
F
S
F
F
F
·
·
·
2
15
16
17
F
1
2
3
1
2
0
–11
ORMAT
0
–11
7-0
F
F
F
7-0
TM
S
F
F
F
·
·
·
14
15
16
0
0
1
2
is
is