LF3321 LODEV [LOGIC Devices Incorporated], LF3321 Datasheet - Page 16

• Manufacturer Part Number: LF3321
• Description: Horizontal Digital Image Filter Improved Performance
• Manufacturer: LODEV [LOGIC Devices Incorporated]

DEVICES INCORPORATED
Single Filter
Mode
Dual Filter
Mode
Matrix-vector
Multiply Mode
LOGIC Devices Incorporated
Operating Modes
In this mode, the device operates as a single FIR filter (see Figure 15). It can be configured to have
as many as 32 taps if symmetric coefficient sets are used. If asymmetric coefficient sets are used, the
device can be configured to have as many as 16 taps. Cascade ports are provided to facilitate cascading
multiple devices to increase the number of filter taps. Bit 1 in Configuration Register 5 determines the
filter mode. In Single Filter Mode, DIN11-0 is the data input for the filter and DOUT15-0 is the data
output for the filter.
In this mode, the device operates as two separate FIR filters (see Figure 16). Each filter can be configured
to have as many as 16 taps if symmetric coefficient sets are used. If asymmetric coefficient sets are used,
each filter can be configured to have as many as 8 taps. In Dual Filter Mode, DIN11-0 is the data input for
Filter A. Either RIN11-0 or DIN11-0 can be the data input for Filter B. The Filter B input is determined by Bit
2 in Configuration Register 5. DOUT15-0 is the data output for Filter A. COUT11-0 and ROUT3-0 together
form the data output for Filter B. COUT11-0 is the twelve least significant bits and ROUT3-0 is the four most
significant bits of the 16-bit Filter B output.
In this mode, the LF3321 can be configured to multiply a square matrix of maximum size N (N = 8 or
16), multiplied by a matrix-vector of maximum size [8,1] or [16,1]. The mathematical representation for
this operation is in Figure 18. When configured in the dual filter mode, the LF3321 can process two matrix-
vector multipliers simultaneously (i.e. [8x8][8x1]). In the single filter mode, the LF3321 can process a single
matrix-vector multiply (i.e. [16x16][16x1]). This mode of operation allows the user to organize data values
(e.g. pixels) into an array (e.g. blocks). This function is useful for any application requiring the operation of
matrix multiplication; a function that is used when generating Discrete Cosine Transform coefficients (DCT)
for the purpose of further processing.
When configuring the LF3321 for an [8x8][8x1] matrix-vector operation, the coefficient banks will require
8 coefficient sets to be loaded into the coefficient memory banks; each coefficient set will have 8, 12-bit
coefficients. The input data, [8x1] column-vector, will be loaded through DIN11-0 for Filter A; either RIN11-0
or DIN11-0 can be the data input for Filter B. Conversely, when configured for a [16x16][16x1] matrix-vector
operation, the coefficient banks will require 16 coefficient sets to be loaded into the coefficient memory
banks; each coefficient set will have 16, 12-bit coefficients. The input data, [16x1] column-vector, will be
loaded through DIN11-0.
Figure 15. Single Filter Mode
Figure 16. Dual Filter Mode
DIN
11-0
ROUT
DIN
11-0
12
11-0
12
12
16
REGISTERS
DOUT
CIRCUIT
FILTER
16
R.S.L.
I/D
A
REGISTERS
15-0
FILTER
I/D
A
DOUT
CIRCUIT
16
RSL
15-0
ROUT
REGISTERS
CIRCUIT
FILTER
16
3-0
R.S.L.
I/D
B
/ COUT
REGISTERS
FILTER
11-0
I/D
B
Horizontal Digital Image Filter
12
12
12
RIN
RIN
COUT
11-0
Improved Performance
11-0
11-0
Video Imaging Products
Feb 5, 2003 LDS.3321-A
LF3321