X4645 INTERSIL [Intersil Corporation], X4645 Datasheet - Page 2

• Manufacturer Part Number: X4645
• Description: CPU Supervidor with 64K EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

PIN CONFIGURATION
PIN FUNCTION
(SOIC)
Pin
1
2
3
4
5
6
7
8
RESET/RESET
(TSSOP)
Pin
3
4
5
6
7
8
1
2
V
V
WP
S
S
SS
CC
S
S
0
1
0
1
8-Pin JEDEC SOIC
8 Pin TSSOP
1
2
3
4
RESET /RESET
1
2
3
4
2
Name
SDA
SCL
V
V
WP
8
7
6
5
S
S
8
7
6
5
CC
SS
0
1
WP
V
SCL
SDA
SCL
SDA
V
RESET/RESET
CC
SS
Device Select Input
Device Select Input
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output
which goes active whenever V
will remain active until V
250ms. RESET/RESET goes active if the Watchdog Timer is enabled and SDA
remains either HIGH or LOW longer than the selectable Watchdog time out pe-
riod. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer.
RESET/RESET goes active on power-up and remains active for 250ms after
the power supply stabilizes.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open
drain or open collector outputs. This pin requires a pull up resistor and the input
buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) re-
starts the Watchdog timer. The absence of a HIGH to LOW transition within the
watchdog time out period results in RESET/RESET going active.
Serial Clock. The Serial Clock controls the serial bus timing for data input and
output.
Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to
the control register.
Supply Voltage
X4643, X4645
CC
rises above the minimum V
CC
falls below the minimum V
Function
CC
sense level for
CC
sense level. It
March 29, 2005
FN8123.0