BD37A19FVM_10 ROHM [Rohm], BD37A19FVM_10 Datasheet - Page 8

• Manufacturer Part Number: BD37A19FVM_10
• Description: Voltage Detector ICs with Watchdog Timer
• Manufacturer: ROHM [Rohm]

●External settings for pins and precautions
●Notes for use
© 2010 ROHM Co., Ltd. All rights reserved.
BD37A19FVM, BD37A41FVM, BD87A28FVM, BD87A29FVM,
BD87A34FVM, BD87A41FVM, BD99A41F
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1) Connect a capacitor (0.001 µF to 1,000 µF) between the VDD and GND pins when the power line impedance is high. Use
2) External capacitance
1) Absolute maximum ratings
2) GND voltage
3) Thermal design
4) Inter-pin shorts and mounting errors
5) Actions in strong electromagnetic field
6) Testing on application boards
7) Regarding input pin of the IC
(Pin A)
of the IC when the power line impedance is high may result in oscillation.
A capacitor must be connected to the CTW pin. When using a large capacitor such as 1 µF, the INH pin must allow a CTW
discharge time of at least 2 ms. The power-on reset time is given by equation [1] on page 5. The WDT time is given by
equations [2] and [3] on page 5, 6. The setting times are proportional to the capacitance value from the equations, so the
maximum and minimum setting times can be calculated from the electrical characteristics according to the capacitance.
Note however that the electrical characteristics do not include the external capacitor's temperature characteristics.
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can
break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any
over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as
fuses.
The potential of GND pin must be minimum potential in all operating conditions.
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any
connection error or if pins are shorted together.
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to
malfunction.
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic
measure. Use similar precaution when transporting or storing the IC.
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example, the relation between each potential is as follows:
Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes
operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.
N
P
○When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
○When GND > Pin B, the P-N junction operates as a parasitic transistor.
P+
Resistor
N
P
GND
Parasitic element
P+
N
(Pin B)
Parasitic element
or transistor
Fig. 18 Example of IC structure
N
P+
C
Transistor (NPN)
8/10
N
B
P substrate
E
GND
P
P+
N
(Pin B)
(Pin A)
B
Technical Note
2010.12 - Rev.A
E
C
GND
Parasitic element
Parasitic element or
transistor