ATA5749_09 ATMEL [ATMEL Corporation], ATA5749_09 Datasheet - Page 12
![no-image](/images/no-image-200.jpg)
ATA5749_09
Manufacturer Part Number
ATA5749_09
Description
Fractional-N PLL Transmitter IC
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATA5749_09.pdf
(26 pages)
6. Configuration Register
6.1
Table 6-1.
12
MSB
LSB
FREQ
ONLY
CLK_
15
[0]
31
General Description
S434_
FSEP
N315
ATA5749 [Preliminary]
14
[7]
30
Organization of the Control Register
FREQ
FSEP
[14]
13
[6]
29
FSEP[0] + ... + FSEP[7]
FREQ
FSEP
[13]
12
[5]
28
The user must program all 32 bits of the configuration register upon power up (EN = HIGH) or
whenever changes to operating parameters are desired. The configuration register bit assign-
ments and descriptions can be found in
Table 6-2.
Name
CLK_ONLY
S434_N315
FREQ[0:14]
FSEP[0:7]
DIV_CNTRL
PWR[0:3]
ASK_NFSK
CLK_ON
FSK Shift = FSEP[0..7]
FREQ
FSEP
[12]
11
[4]
27
FREQ[0] + 2
FREQ
FSEP
[11]
10
[3]
26
Control Register Functional Descriptions
128 = 0..255
FSEP
FREQ
[10]
FREQ[1] + 4
[2]
25
9
Frequency Adjust = FREQ[0..14]
FSEP
FREQ
[1]
15 ... 29
24
[9]
Bit No.
8
7 ... 14
2 ... 5
31
30
6
1
0
FSEP
FREQ
FREQ[2] + ... + FREQ[14]
[0]
23
[8]
7
Table 6-1
Size
CNTRL
15
1
1
8
1
4
1
1
FREQ
DIV_
22
[7]
6
Remarks
Activates/deactivates CLK_ONLY Mode
Low = Normal Mode
High = Clock Only Mode
VCO band selection
High = 367 MHz to 450 MHz
Low = 300 MHz to 368 MHz
PLL frequency adjust
See
FSK deviation adjust
See
CLK output divider ratio
Low = f
High = f
PA output power adjustment
See
Modulation type
Low = FSK
High = ASK
CLK_DRV port control
HIGH = CLK port is ON
LOW = CLK port is OFF
and
PWR[0] + .. + PWR[3]
FREQ
PWR
[3]
21
[6]
5
Output Power = PWR[0..3]
Table 6-1
Table 6-1
Table 4-1
Table
XTO
XTO
/8
FREQ
PWR
/4
[2]
20
[5]
4
6-2.
16384 = 0..32767
for formula
for formula
and
Table 4-2 on page 9
FREQ
PWR
19
[4]
[1]
3
(Figure 4-1 on page
8 = 0..15
FREQ
PWR
18
[3]
[0]
2
FREQ
NFSK
9128D–RKE–01/09
ASK_
17
[2]
1
FREQ
CLK_
7)
ON
16
[1]
0