ATA5278_06 ATMEL [ATMEL Corporation], ATA5278_06 Datasheet - Page 5

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ATA5278_06

Manufacturer Part Number
ATA5278_06
Description
Stand-alone Antenna Driver
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
4832C–RKE–02/06
Figure 3-1.
The startup time, t
cal oscillation build-up times are below 100 µs for ceramic and about 1 ms for crystal resonators.
When using an active clock source, the startup time can be neglected. The internal logic
debounces the first clock signals until it finally powers-up the IC for the time t
this time, the chip select signal S_CS has to be permanently active.
The normal way to bring the chip back into power-down mode is to use an SPI command. Deac-
tivating the chip-select line right after the power-down command, an internal standby timer is
started and will run for t
discharge any energies possibly remaining in the antenna circuit. If the chip-select line is reacti-
vated during this time, the sequence is interrupted and the IC remains in standby mode.
Otherwise, the power-down mode is engaged after the timeout, the oscillator is stopped and the
driver stages are switched to high impedance.
Figure 3-2.
Note that if command 4 is omitted and only the chip-select line is disabled, the ATA5278 stays
operational (i.e., the oscillator keeps running, an eventually running LF data modulation is not
interrupted). Here, only the SPI itself is disabled and the serial bus can be used for other devices
connected to it.
OSCI/OSCO
S_CS
DRV1
Power-up Timing
QSC
Power-down Timing
S_CLK
S_CS
DRV1
S_DI
OSC
startup
, in
timeout
Figure 3-1
= (2048/f
depends on the clock source used in the application. Typi-
f = 8 MHz
OSCI
Z
8 CLK
cmd 4
Oscillation build-up
X
). In this time, the antenna driver stage is stopped to
Legend: Z = high impedance
Figure 3-2
Legend: X = do not care
t
startup
Z = high impedance
illustrates this behavior.
t
timeout
t
deb
Steady oscillation
deb
ATA5278
. Note that during
Z
5

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