X4323 INTERSIL [Intersil Corporation], X4323 Datasheet

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X4323

Manufacturer Part Number
X4323
Description
CPU Supervisor with 32K EEPROM
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet

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Manufacturer
Quantity
Price
Part Number:
X4323
Manufacturer:
XILINX
0
Part Number:
X4323S8-2.7
Manufacturer:
Intersil
Quantity:
850
Part Number:
X4323S8I
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CPU Supervisor with 32K EEPROM
FEATURES
• Selectable watchdog timer
• Low V
• Low power CMOS
• 32Kbits of EEPROM
• Built-in inadvertent write protection
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
BLOCK DIAGRAM
—Four standard reset threshold voltages
—Adjust low V
—Reset signal valid to V
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog off
—3mA active current
—64-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
—Power-up/power-down protection circuitry
—Block Lock (1, 2, 4, 8 pages, all, none)
—8-lead SOIC
—8-lead TSSOP
V
SDA
SCL
special programming sequence
CC
WP
S0
S1
CC
detection and reset assertion
CC
reset threshold voltage using
V
Reset logic
CC
®
Command
Decode &
Register
Control
Threshold
Data
Logic
1
CC
Watchdog Transition
= 1V
Data Sheet
Detector
V
TRIP
EEPROM Array
1-888-INTERSIL or 1-888-352-6832
Protect Logic
Register
+
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Status
-
DESCRIPTION
The X4323/5 combines four popular functions, Power-
on Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Serial EEPROM Memory in one pack-
age. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the RESET/RESET
signal. The user selects the interval from three preset
values. Once selected, the interval does not change,
even after cycling the power.
The device’s low V
user’s system from low voltage conditions, resetting the
system when V
point. RESET/RESET is asserted until V
proper operating level and stabilizes. Four industry
standard V
sil’s unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
Power-on and
March 29, 2005
Timer Reset
Low Voltage
Generation
Watchdog
Watchdog
All other trademarks mentioned are the property of their respective owners.
Timebase
Reset &
Reset
|
TRIP
Intersil (and design) is a registered trademark of Intersil Americas Inc.
CC
thresholds are available, however, Inter-
Copyright Intersil Americas Inc. 2005. All Rights Reserved
falls below the set minimum V
CC
detection circuitry protects the
X4323, X4325
32K, 4K x 8 Bit
RESET (X4323)
RESET (X4325)
CC
FN8122.0
returns to
CC
trip

Related parts for X4323

X4323 Summary of contents

Page 1

... March 29, 2005 DESCRIPTION The X4323/5 combines four popular functions, Power- on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Serial EEPROM Memory in one pack- age. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time ...

Page 2

... SDA 6 8 SCL X4323, X4325 SCL SDA SCL SDA V SS RST/RST Device Select Input Device Select Input Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever V falls below the minimum V ...

Page 3

... PRINCIPLES OF OPERATION Power-on Reset Application of power to the X4323/5 activates a Power-on Reset Circuit that pulls the RESET/RESET pin active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. – It prevents the processor from operating prior to sta- bilization of the oscillator. – ...

Page 4

... A0h Figure 3. Sample V Reset Circuit TRIP 4.7K RESET V TRIP Adj. 4 X4323, X4325 Resetting the higher or This procedure is used to set the V TRIP voltage level. For example, if the current V and the new V be reset. When V thing less than 1.7V. This procedure must be used to TRIP set the voltage to a lower value ...

Page 5

... See "Writing to the Control Register" below. The user must issue a stop after sending this byte to the register to initiate the nonvolatile cycle that stores WD1, and WD0. The X4323/5 will not acknowledge any data bytes written after the first byte is entered. New V Applied = ...

Page 6

... The state of the Control Register can be read at any time by performing a random read at address FFFFh. Only one byte is read by each register read operation. The X4323/5 resets itself after the first byte is read. The master should supply a stop condition to be con- sistent with the bus protocol, but a stop is not required to end this operation ...

Page 7

... Figure 5. Valid Data Changes on the SDA Bus SCL SDA 7 X4323, X4325 – The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. To illustrate, a sequence of writes to the device con- sisting of [02H, 06H, 02H] will reset all of the nonvola- tile bits in the Control Register to 0 ...

Page 8

... Data Output from Receiver Start 8 X4323, X4325 Serial Stop Condition All communications must be terminated by a stop con- dition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence ...

Page 9

... Signals from the Slave 9 X4323, X4325 eight bits of data. After receiving the 8-bits of the Data Byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the inter- nal write cycle to the nonvolatile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master ...

Page 10

... ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. Refer to the flow chart in Figure 11. 10 X4323, X4325 Address Pointer Address Ends Here 60 Addr = 8 Figure 11 ...

Page 11

... Signals from the Slave 11 X4323, X4325 Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the Data Byte. The master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition ...

Page 12

... When the R/W bit is a one, then a read operation is selected. A zero selects a write operation. Refer to Figure 15. 12 X4323, X4325 ing it requires additional data. The device continues to output data for each acknowledge received. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition ...

Page 13

... Figure 15. X4323/5 Addressing Device Identifier (X1) (X0 Operational Notes The device powers-up in the following state: – The device is in the low power standby state. – The WEL bit is set to ‘0’. In this state it is not possi- ble to write to the device. ...

Page 14

... Device Select Bits in the Slave Address Byte. (3) V Min. and V Max. are for reference only and are not tested X4323, X4325 COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. .... -1.0V to +7V This is a stress rating only; functional operation of the SS ...

Page 15

... Cb Capacitive load for each bus line Notes: (1) Typical values are for T = 25°C and total capacitance of one bus line in pF. 15 X4323, X4325 = 5V) CC Parameter A.C. TEST CONDITIONS Input pulse levels Input rise and fall times Input and output timing levels = 0 ...

Page 16

... the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 16 X4323, X4325 t t HIGH LOW ...

Page 17

... R RESET (X4323) RESET (X4325) RESET Output Timing Symbol V Reset Trip Point Voltage, X4323/5-4.5A TRIP Reset Trip Point Voltage, X4323/5 Reset Trip Point Voltage, X4323/5-2.7A Reset Trip Point Voltage, X4323/5-2.7 t Power-up Reset Time OUT PURST ( Detect to Reset/Output RPD CC ( Fall Time ...

Page 18

... Program Voltage repeatability (Successive program operations. Programmed at tr TRIP 25°C Program variation after programming (0-75°C). (Programmed at 25°C.) tv TRIP V programming parameters are periodically sampled and are not 100% tested. TRIP 18 X4323, X4325 Min. 100 450 1 100 V TRIP t TSU 01h or 03h 00h 00h ...

Page 19

... PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0° - 8° 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 19 X4323, X4325 Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.050 (1.27) X 45° 0.0075 (0.19) 0.250" 0.010 (0.25) FOOTPRINT 0 ...

Page 20

... PACKAGING INFORMATION 0° - 8° See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 20 X4323, X4325 8-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 (4.3) .177 (4.5) .114 (2.9) .122 (3.1) .047 (1.20) .0075 (.19) .002 (.05) .006 (.15) .0118 (.30) .010 (.25) Gage Plane Seating Plane .019 (.50) .029 (.75) Detail A (20X) ...

Page 21

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 21 X4323, X4325 Operating Part Number RESET Temperature Range (Active LOW) 0° ...

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