X5329 INTERSIL [Intersil Corporation], X5329 Datasheet - Page 14
X5329
Manufacturer Part Number
X5329
Description
CPU Supervisor with 32Kbit SPI EEPROM
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
1.X5329.pdf
(21 pages)
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Serial Input Timing
Serial Output Timing
Notes: (3) This parameter is periodically sampled and not 100% tested.
Serial Output Timing
Symbol
t
t
f
RO
FO
t
t
SCK
SCK
(4) t
SCK
DIS
HO
t
SO
CS
SO
CS
V
(3)
(3)
SI
SI
write cycle.
WC
is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
LSB IN
ADDR
Clock Frequency
Output Disable Time
Output Valid from Clock Low
Output Hold Time
Output Rise Time
Output Fall Time
t
SU
High Impedance
MSB IN
14
MSB Out
t
LEAD
t
V
t
H
t
CYC
MSB–1 Out
Parameter
X5328, X5329
t
HO
t
RI
t
WH
t
WL
Min.
t
FI
0
0
LSB IN
LSB Out
2.7-5.5V
t
CS
Max.
250
250
100
100
2
t
LAG
t
t
DIS
LAG
October 17, 2005
Unit
MHz
ns
ns
ns
ns
ns
FN8132.1