X40011 XICOR [Xicor Inc.], X40011 Datasheet
X40011
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X40011 Summary of contents
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... Reset Logic Register Status Register Low Voltage + Generation - V V2MON TRIP1 *X40010/11 = V2MON* TRIP2 X40014/ www.xicor.com activates the power on reset CC point. RESET/ TRIP1 returns to proper operating CC and WDO RESET X40010/14 Power on, RESET Reset X40011/15 V2FAIL Characteristics subject to change without notice ...
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... V2MON comparator is supplied by V2MON (X40010/11 (X40014/15 RESET/ RESET Output. (X40011/15) This is an active LOW, open drain output which goes active when- ever V RESET CC thereafter. RESET Output. (X40010/14) This is an active HIGH CMOS output which goes active whenever ...
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... When V exceeds the device V CC TRIP1 t (selectable) the circuit releases the RESET PURST (X40011) and RESET (X40010) pin allowing the system to begin operation. Low Voltage V (V1 Monitoring) CC During operation, the X40010/11/14/15 monitors the V level and asserts RESET/RESET if supply voltage falls below a preset minimum V ...
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... X40010/X40011/X40014/X40015 – Preliminary Figure 2. V Set/Reset Conditions TRIPX V TRIPX WDO 0 SCL SDA A0h WATCHDOG TIMER The Watchdog Timer circuit monitors the microproces- sor activity by monitoring the SDA and SCL pins. The microprocessor must toggle the SDA pin HIGH to LOW periodically, while SCL also toggles from HIGH to LOW ...
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... X40010/X40011/X40014/X40015 – Preliminary Setting a Lower V Voltage (x=1, 2) TRIPx In order to set lower voltage than the TRIPx present value, then V must first be “reset” accord- TRIPx ing to the procedure described below. Once V has been “reset”, then V can be set to the desired TRIPx voltage using the procedure described in “Setting a Higher V Voltage” ...
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... X40010/X40011/X40014/X40015 – Preliminary Figure 5. V Set/Reset Sequence ( TRIPX New V applied = X Old V applied + | Error | X Error < MDE WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a vola- tile latch that powers up in the LOW (disabled) state. ...
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... X40010/X40011/X40014/X40015 – Preliminary PUP1, PUP0: Power Up Bits (Nonvolatile) The Power Up bits, PUP1 and PUP0, determine the time delay. The nominal power up times are t PURST shown in the following table. PUP1 PUP0 Power on Reset Delay ( 200ms (factory setting 400ms 1 1 800ms ...
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... X40010/X40011/X40014/X40015 – Preliminary Figure 6. Valid Data Changes on the SDA Bus SCL SDA At power-up, the Fault Detection Register is defaulted to all “0”. The system needs to initialize this register to all “1” before the actual monitoring take place. In the event of any one of the monitored sources failed. The corresponding bits in the register will change from a “ ...
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... X40010/X40011/X40014/X40015 – Preliminary Figure 7. Valid Start and Stop Conditions SCL SDA Serial Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data ...
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... X40010/X40011/X40014/X40015 – Preliminary Read Operation Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a “dummy” write operation. The master issues the start condition and the Slave Address Byte, receives an acknowledge, then issues the Word Address Bytes. After acknowledging receipts of the Word Address Bytes, the master immedi- Figure 9 ...
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... X40010/X40011/X40014/X40015 – Preliminary Figure 10. Acknowledge Polling Sequence Byte Load Completed by Issuing STOP. Enter ACK Polling Issue START Issue Slave Address Byte (Read or Write) ACK Returned? YES High Voltage Cycle Complete. Continue Command Sequence? YES Continue Normal Read or Write Command Sequence PROCEED It should be noted that the ninth clock cycle of the read operation is not a “ ...
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... X40010/X40011/X40014/X40015 – Preliminary SERIAL DEVICE ADDRESSING Memory Address Map CR, Control Register, CR7: CR0 Address: 1FF hex FDR, Fault DetectionRegister, FDR7: FDR0 Address: 0FF hex Slave Address Byte Following a start condition, the master must output a Slave Address Byte. This byte consists of several parts: – ...
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... X40010/X40011/X40014/X40015 – Preliminary – One bit of the slave command byte is a R/W bit. The R/W bit of the Slave Address Byte defines the opera- tion to be performed. When the R/W bit is a one, then a read operation is selected. A zero selects a write operation. Word Address The word address is either supplied by the master or obtained from an internal counter. The internal counter is undefi ...
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... X40010/X40011/X40014/X40015 – Preliminary ABSOLUTE MAXIMUM RATINGS Temperature under bias ................... –65°C to +135°C Storage temperature ........................ –65°C to +150°C Voltage on any pin with respect to V ......................................–1.0V to +7V SS D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds)........ 300°C RECOMMENDED OPERATING CONDITIONS Temperature Min. ...
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... X40010/X40011/X40014/X40015 – Preliminary D.C. OPERATING CHARACTERISTICS (Continued) (Over the recommended operating conditions unless otherwise specified) Symbol Parameter V Supply CC ( Trip Point Voltage Range TRIP1 CC ( V2FAIL RPD2 TRIP2 Second Supply Monitor I V2MON Current V2 (5) V V2MON Trip Point Voltage Range ...
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... X40010/X40011/X40014/X40015 – Preliminary EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR OUT 4.6K 2.06K RESET SDA WDO 30pF 30pF A.C. TEST CONDITIONS Input pulse levels V Input rise and fall times 10ns V Input and output timing levels Output load Standard output load REV 1.3.4 7/12/02 SYMBOL TABLE ...
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... X40010/X40011/X40014/X40015 – Preliminary A.C. CHARACTERISTICS Symbol f SCL Clock Frequency SCL t Pulse width Suppression Time at inputs IN t SCL LOW to SDA Data Out Valid AA t Time the bus free before start of new transmission BUF t Clock LOW Time LOW t Clock HIGH Time HIGH t Start Condition Setup Time ...
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... X40010/X40011/X40014/X40015 – Preliminary Write Cycle Timing SCL SDA th 8 Bit of Last Byte Nonvolatile Write Cycle Timing Symbol (1) t Write Cycle Time WC Note: ( the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. ...
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... X40010/X40011/X40014/X40015 – Preliminary RESET/RESET Timings V TRIP1 RESET V RVALID RESET LOW VOLTAGE AND WATCHDOG TIMING PARAMETERS Symbol ( RESET/RESET (Power down only) RPD1 TRIP1 ( V2FAIL RPDX TRIP2 Power On Reset delay: t PURST PUP1=0, PUP0=0 PUP1=0, PUP0=1 (factory setting) ...
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... X40010/X40011/X40014/X40015 – Preliminary Watchdog Time Out For 2-Wire Interface Start SCL SDA WDO Minimum Sequence to Reset WDT SCL SDA V Set/Reset Conditions TRIPX (V TRIPX t TSU WDO t VPS SCL 0 SDA A0h Start REV 1.3.4 7/12/02 Start Clockin ( RSP < t WDO Start V /V2MON ) ...
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... X40010/X40011/X40014/X40015 – Preliminary Programming Specifications: V TRIP1 TRIP2 Parameter t WDO Program Voltage Setup time VPS t WDO Program Voltage Hold time VPH t V Level Setup time TSU TRIPX t V Level Hold (stable) time THD TRIPX t V Program Cycle WC TRIPX t Program Voltage Off time before next cycle ...
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... X40010/X40011/X40014/X40015 – Preliminary PACKAGING INFORMATION Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0° - 8° 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.3.4 7/12/02 8-Lead Plastic, SOIC, Package Code S8 Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.050 (1.27) X 45° 0.0075 (0.19) 0.010 (0.25) FOOTPRINT www.xicor.com ...
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... X40010/X40011/X40014/X40015 – Preliminary PACKAGING INFORMATION 0° – 8° Detail A (20X) See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.3.4 7/12/02 8-Lead Plastic, TSSOP, Package Code V8 .025 (.65) BSC .169 (4.3) .177 (4.5) .114 (2.9) .122 (3.1) .047 (1.20) .0075 (.19) .002 (.05) .006 (.15) .0118 (.30) .010 (.25) Gage Plane Seating Plane ...
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... X40010/X40011/X40014/X40015 – Preliminary ORDERING INFORMATION TRIP1 Range Range V TRIP2 2.9-5.5 4.6V±50mV 2.9V±50mV 2.6-5.5 4.4V±50mV 2.6V±50mV 1.7-3.6 2.9V±50mV 1.7V±50mV 1.3-3.6 2.9V±50mV 1.3V±50mV 1.3-3.6 2.6V±50mV 1.3V±50mV 1.0-3.6 2.9V±50mV 1.0V±50mV PART MARK INFORMATION REV 1.3.4 7/12/02 Operating Temperature Range Package Range o 8L SOIC - TSSOP - ...
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... X40010/X40011/X40014/X40015 – Preliminary LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. ...