W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 15

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

Pins Description, Continued
Ethernet Interface (1)
MDC1
MDIO1
COL1
CRS1
TX1_CLK
TX1D [3:0] /
R1A_TXD [1:0]
TX1_EN/
R1A_TXEN
RX1_CLK /
R1A_REFCLK
RX1D [3:0] /
R1A_RXD[1:0]
RX1_DV/
R1A_CRSDV
RX1_ERR /
R1A_RXERR
PIN NAME
IO TYPE
IOU
IU
IU
IU
IU
IU
IU
IU
O
O
O
MII Management Data Clock for Ethernet 1. It is the reference clock of MDIO1. Each
MDIO1 data will be latched at the rising edge of MDC1 clock.
MII Management Data I/O for Ethernet 1. It is used to transfer MII control and status
information between PHY and MAC.
Collision Detect for Ethernet 1 in MII mode. This shall be asserted by PHY upon
detecting a collision happened over the medium. It will be asserted and lasted until
collision condition vanishes.
Carrier Sense for Ethernet 1 in MII mode.
Transmit Data Clock for Ethernet 1 in MII mode, TX1_CLK is driven by PHY and
provides the timing reference for TX1_EN and TX1D. The clock will be 25MHz or 2.5
MHz.
Transmit Data bus (4-bit) for Ethernet 1 in MII mode. The nibble transmit data bus is
synchronized with TX1_CLK. It should be latched by PHY at the rising edge of
TX1_CLK.
In RMII mode, TX1D [1:0] are used as R1A_TXD [1:0], 2-bit Transmit Data bus for
Ethernet 1.
Transmit Enable for Ethernet 1 in MII and RMII mode. It indicates the transmit
activity to external PHY. It will be synchronized with TX1_CLK in MII mode.
Receive Data Clock for Ethernet 1 in MII mode. When it is used as a received clock
pin, it is from PHY. The clock will be either 25 MHz or 2.5 MHz. The minimum duty
cycle at its high or low state should be 35% of the nominal period for all conditions.
In RMII mode, this pin is used as R1A_REFCLK. The clock shall be 50MHz +/-50 ppm
with minimum 35% duty cycle at high or low state.
Receive Data bus (4-bit) for Ethernet 1 in MII mode. They are driven by external
PHY, and should be synchronized with RX1_CLK and valid only when RX1_DV is
valid.
In RMII mode, RX1D [1:0] are used as R1A_RXD [1:0], 2-bit Receive Data bus for
Ethernet 1.
Receive Data Valid for Ethernet 1 in MII mode. It will be asserted when received data is
coming and present, and de-asserted at the end of the frame.
In RMII mode, this pin is used as the R1A_CRSDV, Carrier Sense / Receive Data Valid
for Ethernet 1. The R1A_CRSDV shall be asserted by PHY when the receive medium
is non-idle. Loss of carrier shall result in the de-assertion of R1A_CRSDV synchronous
to the cycle of R1A_REFCLK, and only on nibble boundaries.
Receive Data Error for Ethernet 1 in MII and RMII mode. It indicates a data error
detected by PHY. The assertion should be lasted for longer than a period of RX0_CLK.
When RX0_ERR is asserted, the MAC will report a CRC error.
- 15 -
W90N740 Reference Manual
DESCRIPTION
Publication Release Date: May 9, 2003
Revision A2