Z86C8316PEC ZILOG [Zilog, Inc.], Z86C8316PEC Datasheet - Page 42

• Manufacturer Part Number: Z86C8316PEC
• Description: Z8 MCU MICROCONTROLLERS
• Manufacturer: ZILOG [Zilog, Inc.]

Z86C83/C84
Z8
42
R248 P01M
R246 P2M
*Default Setting After Reset
R247 P3M
*Default Setting After Reset
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6
Figure 57. Port 3 Mode Register (F7
Figure 58. Port 2 Mode Register (F6
®
MCU Microcontrollers
† Not available for
Z86C82, but must be set to 00.
D5 D4
Figure 59. Port 0 and 1 Mode Register
D3 D2
(F8
D1 D0
H
: Write-Only)
0 Port 2 Open-Drain*
1 Port 2 Push-Pull
Port 3 Inputs
0 Digital*
1 Analog
Reserved (Must be 0)
Reserved (Must be 1)
P00-P03 Mode †
Reserved (Must be 0)
P04-P06 Mode †
P27- P20 I/O Definition
00 Output
01 Input *
1X A11-A8
00 Output
01 Input *
1X A15-A12
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT*
H
H
: Write-Only)
: Write-Only)
Figure 60. Interrupt Priority Register (F9
R251 IMR
R249 IPR
R250 IRQ
Figure 62. Interrupt Mask Register (F
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
† This option must be selected when
ROM code is submitted for Rom Masking;
otherwise, this control bit is disabled
permanently.
Default Setting After Reset = 00H
Figure 61. Interrupt Request Register
(F
AH
: Read/Write)
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = Software Controlled
IRQ4 = T0
IRQ5 = T1
Inter Edge
1 Enables IRQ5-IRQ0
1 RAM Protect Enabled †
0 RAM Protect Disabled *
1 Enables Interrupts
0 Disable interrupts *
00 P31
01 P31
10 P31
11 P31
Reserved (Must be 0)
Interrupt Group Priority
IRQ1, IRQ4 Priority (Group C)
IRQ0, IRQ2 Priority (Group B)
IRQ3, IRQ5 Priority (Group A)
* (Default setting after RESET.)
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
(D0 = IRQ0)
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
P32
P32
P32
P32
BH
: Read/Write)
DS96DZ80203
H
: Write-Only)