W78E52BF-40 WINBOND [Winbond], W78E52BF-40 Datasheet - Page 10

• Manufacturer Part Number: W78E52BF-40
• Description: 8-BIT MTP MICROCONTROLLER
• Manufacturer: WINBOND [Winbond]

Program/Erase Inhibit Operation
This operation allows parallel erasing or programming of multiple chips with different data. When
P3.6( CE ) = V
except for the P3.6 and P3.7 pins, the individual chips may have common inputs.
Company/Device ID Read Operation
This operation is supported for MTP ROM programmer to get the company ID or device ID on the
W78E52B.
Notes:
1. All these operations happen in RST = V
2. V
3. The program verify operation follows behind the program operation.
4. This erase operation will erase all the on-chip MTP-ROM cells and the Security bits.
5. The erase verify operation follows behind the erase operation.
SECURITY BITS
During the on-chip MTP-ROM operation mode, the MTP-ROM can be programmed and verified
repeatedly. Until the code inside the MTP-ROM is confirmed OK, the code can be protected. The
protection of MTP ROM and those operations on it are described below.
The W78E52B has several Special Setting Registers, including the Security Register and
Company/Device ID Registers, which can not be accessed in normal mode. These registers can only
be accessed from the MTP-ROM operation mode. Those bits of the Security Registers can not be
changed once they have been programmed from high to low. They can only be reset through erase-
all operation. The contents of the Company ID and Device ID registers have been set in factory. Both
registers are addressed by the A0 address line during the same specific condition. The Security
Register is addressed in the MTP-ROM operation mode by address #0FFFFh.
Read
Output Disable
Program
Program Verify
Erase
Erase Verify
Program/Erase
Inhibit
Company ID
Device ID
OPERATIONS P3.0
CP
= 12.5V, V
EP
IH
= 14.5V, V
CTRL)
, P3.7( OE ) = V
(A9
X
0
0
0
0
1
1
1
1
IH
CTRL)
(A13
P3.1
= V
0
0
0
0
0
0
0
0
0
DD
, V
CTRL)
IH
IL
IH
(A14
P3.2
, ALE = V
= Vss.
0
0
0
0
0
0
0
0
0
, erasing or programming of non-targeted chips is inhibited. So,
CTRL)
IL
P3.3
(OE
and PSEN = V
0
0
0
0
0
0
0
0
0
- 10 -
( CE )
P3.6
0
0
0
1
0
1
1
0
0
IH
.
( OE )
P3.7
0
1
1
0
1
0
1
0
0
Preliminary W78E52B
(V
V
V
V
V
V
V
EA
CP
1
1
1
1
CP
CP
EP
EP
EP
PP
/
)
(A15..A0)
others: X
Address
Address
Address
Address
A0 = 0
A0 = 1
P2,P1
A0:0,
X
X
Data Out
Data Out
Data Out
Data Out
Data Out
(D7..D0)
Data In
Data In
0FFH
Hi-Z
P0
X
NOTE
@3
@4
@5