EP7312-CB-90 CIRRUS [Cirrus Logic], EP7312-CB-90 Datasheet - Page 8

• Manufacturer Part Number: EP7312-CB-90
• Description: HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE
• Manufacturer: CIRRUS [Cirrus Logic]

EP7312
High-Performance, Low-Power System on Chip
CODEC Interface
The EP7312 includes an interface to telephony-type
CODECs for easy integration into voice-over-IP and
other voice communications systems. The CODEC
interface is multiplexed to the same pins as the DAI and
SSI2.
Assignments.
SSI2 Interface
An additional SPI/Microwire1-compatible interface is
available
communications. The SSI2 unit shares the same pins as
the DAI and CODEC interfaces through a multiplexer.
The SSI2 Interface has these features:
• Synchronous clock speeds of up to 512 kHz
• Separate 16 entry TX and RX half-word wide FIFOs
• Half empty/full interrupts for FIFOs
• Separate RX and TX frame sync signals for
Table 7
8
PCMCLK
PCMOUT
PCMIN
PCMSYNC
SSICLK
SSITXDA
SSIRXDA
SSITXFR
SSIRXFR
Note:
asymmetric traffic
Note:
Pin Mnemonic
Pin Mnemonic
Table 6
shows the SSI2 Interface pin assignments.
See
multiplexes.
See
multiplexes.
Table 6. CODEC Interface Pin Assignments
Table 7. SSI2 Interface Pin Assignments
for
Table 18 on page 11
Table 18 on page 11
shows the CODEC Interface Pin
both
I/O
master
O
O
O
I
I/O
I/O
I/O
I/O
O
I
for information on pin
for information on pin
Serial data in
Serial bit clock
Serial data out
Frame sync
Serial bit clock
Serial data out
Serial data in
Transmit frame sync
Receive frame sync
and
Pin Description
Pin Description
©
slave
C opyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
mode
Synchronous Serial Interface
The EP7312 Synchronous Serial Interface has these
features:
• ADC (SSI) Interface: Master mode only; SPI and
• Selectable serial clock polarity
Table 8
assignments.
LCD Controller
A DMA address generator is provided that fetches video
display data for the LCD controller from memory. The
display frame buffer start address is programmable,
allowing the LCD frame buffer to be in SDRAM, internal
SRAM or external SRAM. The LCD controller has these
features:
• Interfaces directly to a single-scan panel monochrome
• Interfaces to a single-scan panel color STN LCD with
• Panel width size is programmable from 32 to 1024
• Video frame buffer size programmable up to
• Bits per pixel of 1, 2, or 4 bits
Table 9
ADCLK
ADCIN
ADCOUT
nADCCS
SMPCLK
CL1
CL2
DD[3:0]
FRM
M
Pin Mnemonic
Microwire1-compatible (128 kbps operation)
STN LCD
minimal external glue logic
pixels in 16-pixel increments
128 KB
Pin Mnemonic
shows the LCD Interface pin assignments.
shows the Synchronous Serial Interface pin
Table 8. Serial Interface Pin Assignments
Table 9. LCD Interface Pin Assignments
I/O
O
O
O
O
O
I/O
O
O
O
O
I
LCD line clock
LCD pixel clock out
LCD serial display data bus
LCD frame synchronization pulse
LCD AC bias drive
SSI1 ADC serial clock
SSI1 ADC serial input
SSI1 ADC serial output
SSI1 ADC chip select
SSI1 ADC sample clock
Pin Description
Pin Description
DS508PP5