EP7311-CB-C CIRRUS [Cirrus Logic], EP7311-CB-C Datasheet - Page 22

no-image

EP7311-CB-C

Manufacturer Part Number
EP7311-CB-C
Description
HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE
Manufacturer
CIRRUS [Cirrus Logic]
Datasheet
EP7311
High-Performance, Low-Power System on Chip
Static Memory Burst Write Cycle
22
EXPRDY
EXPCLK
WRITE
WORD
WORD
nMWE
nMOE
HALF
nCS
A
D
Note:
1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
4. Address, Data, Halfword, Word, and Write hold state until next cycle.
t
t
HWd
WDd
t
EXs
t
MWd
t
t
t
CSd
Ad
Dv
Figure 10. Static Memory Burst Write Cycle Timing Measurement
t
Dnv
©
t
EXh
C opyright Cirrus Logic, Inc. 2003
t
Ah
t
MWh
(All Rights Reserved)
t
t
MWd
Dv
t
Dnv
t
Ah
t
MWh
t
t
MWd
Dv
t
Dnv
t
Ah
t
MWh
t
t
MWd
Dv
t
MWh
DS506PP1
t
CSh

Related parts for EP7311-CB-C