DS87C530-ENL+ DALLAS [Dallas Semiconductor], DS87C530-ENL+ Datasheet - Page 34

• Manufacturer Part Number: DS87C530-ENL+
• Description: EPROM/ROM Microcontrollers with Real-Time Clock
• Manufacturer: DALLAS [Dallas Semiconductor]

DC ELECTRICAL CHARACTERISTICS (continued)
(V
TYPICAL I
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Input Leakage Port 0, EA , Pins, I/O Mode
Input Leakage Port 0, Bus Mode
RST Pulldown Resistance
CC
= 4.5V to 5.5V, T
Storage temperature is defined as the temperature of the device when V
SRAM are not battery backed and are undefined.
All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
All voltages are referenced to ground.
Active current measured with 33MHz clock source on XTAL1, V
Idle mode current measured with 33MHz clock source on XTAL1, V
Stop mode current measured with XTAL1 and RST grounded, V
V
RST = V
I/O mode.
During a 0-to-1 transition, a one-shot drives the ports hard for two clock cycles. This measurement reflects port in transition
mode.
When addressing external memory. This specification only applies to the first clock cycle following the transition.
This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding port latch bit is
set to 1. This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin will also have to overcome the
transition current.
Ports 1, 2, and 3 source transition current when being pulled down externally. It reaches its maximum at approximately 2V.
0.45 < V
0.45 < V
the input transition point of the latch, approximately 2V.
CC
CC
= 0V, V
vs. FREQUENCY
PARAMETER
IN
IN
CC
< V
< V
. This condition mimics operation of pins in I/O mode. Port 0 is tri-stated in reset and when at a logic high state during
BAT
A
CC
CC
= 3.3V. 32.768kHz crystal with 12.5pF load capacitance between RTCX1 and RTCX2 pins. RTCE bit set to 1.
= -40°C to +85°C.)
. RST = V
. Not a high-impedance input. This port is a weak address holding latch in Bus Mode. Peak current occurs near
CC
. This condition mimics operation of pins in I/O mode.
SYMBOL
R
34 of 47
I
I
RST
L
L
CC
CC
= RST = 5.5V, other pins disconnected.
= 5.5V, all other pins disconnected.
MIN
CC
-300
-10
50
= 5.5V, RST at ground, other pins disconnected.
CC
= 0V and V
TYP
BAT
= 0V. In this state, the contents of
MAX
+300
+10
200
UNITS
m A
m A
k W
NOTES
13
14