COP8AME9ENA8 NSC [National Semiconductor], COP8AME9ENA8 Datasheet
COP8AME9ENA8
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COP8AME9ENA8 Summary of contents
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COP8AME9 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEPROM, Temperature Sensor, 10-Bit A/D and Brownout Reset 1.0 General Description The COP8AME9 Flash microcontroller is a highly integrated COP8 ™ Feature core device, with 8k Flash memory ...
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Block Diagram 4.0 Ordering Information COP8 AM Family and Feature Set Indicator AM = 4.17V - 4.5V Brownout www.national.com Part Numbering Scheme Program Program Memory Memory No. Of Pins Size Type ...
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General Description ..................................................................................................................................... 1 2.0 Features ....................................................................................................................................................... 1 3.0 Block Diagram .............................................................................................................................................. 2 4.0 Ordering Information .................................................................................................................................... 2 5.0 Connection Diagram .................................................................................................................................... 6 6.0 Architectural Overview ................................................................................................................................. 8 6.1 EMI REDUCTION ...................................................................................................................................... 8 6.2 IN-SYSTEM PROGRAMMING AND VIRTUAL EEPROM ...
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ITMR Register .................................................................................................................................. 31 12.2 TIMER T1, TIMER T2, AND TIMER T3 ................................................................................................ 31 12.2.1 Timer Operating Speeds .................................................................................................................. 31 12.2.2 Mode 1. Processor Independent PWM Mode ................................................................................. 31 12.2.3 Mode 2. External Event Counter Mode ........................................................................................... 32 12.2.4 ...
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Programmable Gain Amplifier Settling Time ................................................................................... 52 15.2.2 Programmable Gain Amplifier Offset Calibration ............................................................................. 53 15.2.3 Trimming the Offset on the Programmable Gain Amplifier ............................................................. 53 15.3 A/D OPERATION ................................................................................................................................... 54 15.3.1 Prescaler .......................................................................................................................................... 54 15.4 ANALOG INPUT AND ...
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Connection Diagram www.national.com 20006364 Top View See NS Package Number M28B or N28B 6 ...
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Port Type L0 I/O MIWU or Low Speed OSC In L1 I/O MIWU or CKX or Low Speed OSC Out L2 I/O MIWU or TDX L3 I/O MIWU or RDX L4 I/O MIWU or T2A L5 I/O MIWU or T2B ...
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Architectural Overview 6.1 EMI REDUCTION The COP8AME9 device incorporates circuitry that guards against electromagnetic interference - an increasing problem in today’s microcontroller board designs. National’s patented EMI reduction technology offers low EMI clock circuitry, gradual turn-on output drivers (GTOs) ...
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Architectural Overview examples. In many cases, the instruction set can simulta- neously execute as many as three functions with the same single-byte instruction. JID: (Jump Indirect); Single byte instruction decodes exter- nal events and jumps to corresponding service routines ...
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Absolute Maximum Ratings 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin Total Current into V Pin (Source) CC 8.0 ...
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Electrical Characteristics DC Electrical Characteristics (−40˚C ≤ T Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Output Current Levels Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) (Note 7) Allowable Sink Current ...
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AC Electrical Characteristics (−40˚C ≤ T Note 3: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to V and outputs driven low but not ...
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Stand-alone Amplifier Electrical Characteristics (4.5V ≤ AV ≤ T ≤ +85˚C) A Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Input Offset Voltage Input Common Mode Capacitance 0V ≤ V Common Mode Rejection Ratio (CMRR) ...
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Programmable Gain Amplifier Electrical Characteristics (4.5V ≤ AV 5.5V, −40˚C ≤ T ≤ +85˚C) A Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Output Swing Low Supply Current on AV when CC enabled Enable Time ...
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Pin Descriptions The COP8AME9 I/O structure enables designers to recon- figure the microcontroller’s I/O functions with a single in- struction. Each individual I/O pin can be independently con- figured as output pin low, output high, input with high impedance ...
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Pin Descriptions Speed Oscillator Output) L0 Multi-Input Wake-up (Low Speed Oscillator Input) FIGURE 2. I/O Port Configurations FIGURE 3. I/O Port Configurations — Output Mode FIGURE 4. I/O Port Configurations — Input Mode 9.1 EMULATION CONNECTION Connection to the ...
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Functional Description (Continued) 10.2 PROGRAM MEMORY The program memory consists of 8192 bytes of Flash Memory. These bytes may hold program instructions or con- stant data (data tables for the LAID instruction, jump vectors for the JID instruction, and ...
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Functional Description 10.4.1 Virtual EEPROM The Flash memory and the User ISP functions (see Section 5.7), provide the user with the capability to use the flash program memory to back up user defined sections of RAM. This effectively provides ...
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Functional Description (Continued) ;options .endsect Example: The following sets a value in the Option Register for a COP8AME9. The Option Register bit values shown select options: Security disabled, WATCHDOG enabled HALT mode enabled and execution will commence from Flash ...
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Functional Description (Continued) WATCHDOG (if enabled): The device comes out of reset with both the WATCHDOG logic and the Clock Monitor detector armed, with the WATCHDOG service window bits set and the Clock Moni- tor bit set. The WATCHDOG ...
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Functional Description FIGURE 10. Reset Circuit Using Power-On Reset 10.8 OSCILLATOR CIRCUITS The device has two crystal oscillators to facilitate low power operation while maintaining throughput when required. Fur- ther information on the use of the two oscillators is ...
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Functional Description (Continued) The crystal and other oscillator components should be placed in close proximity to the CKI and CKO pins to mini- mize printed circuit trace length. The values for the external capacitors should be chosen to obtain ...
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Functional Description (Continued) flags. In addition to the SC and R/C instructions, ADC, SUBC, RRC and RLC instructions affect the Carry and Half Carry flags. 10.9.3 ICNTRL Register (Address X'00E8) Unused LPEN T0PND T0EN µWPND µWEN Bit 7 The ...
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In-System Programming 11.1 INTRODUCTION This device provides the capability to program the program memory while installed in an application board. This feature is called In System Programming (ISP). It provides a means of ISP by using the MICROWIRE/PLUS, or ...
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In-System Programming (Continued) 11.3.4 ISP Write Timing Register The Write Timing Register (PGMTIM) is used to control the width of the timing pulses for write and erase operations. The value to be written into this register is dependent on ...
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In-System Programming (Continued) TABLE 9. KEY Register Write Format KEY When Writing Bit 7 Bit 6 Bit 5 Bit 4 Bit Bits 7–2: Key value that must be written to set the KEY ...
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In-System Programming (Continued) The following table lists the MICROWIRE/PLUS ISP com- mands and provides information on required parameters and return values. Command Function PGMTIM_SET Write Pulse Timing Register PAGE_ERASE Page Erase MASS_ERASE Mass Erase READ_BYTE Read Byte BLOCKR Block ...
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In-System Programming Command/ Command Function Label Entry Point cpgerase Page Erase 0x17 cmserase Mass Erase 0x1A creadbf Read Byte 0x11 cblockr Block Read 0x26 cwritebf Write Byte 0x14 cblockw Block Write 0x23 exit EXIT 0x62 uwisp MICROWIRE/ 0x00 PLUS ...
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In-System Programming Register Name ISPADHI High byte of Flash Memory Address ISPADLO Low byte of Flash Memory Address ISPWR The user must store the byte to be written into this register before jumping into the write byte routine. ISPRD ...
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Timers The device contains a very versatile set of timers (T0, T1, T2 and T3). Timers T1, T2 and T3 and associated autoreload/ capture registers power up containing random data. 12.1 TIMER T0 (IDLE TIMER) The device supports applications ...
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Timers (Continued) 12.1.1 ITMR Register CCK LSON HSON DCEN RSVD ITSEL2 ITSEL1 ITSEL0 SEL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bits 7–4: Described in Section 13.0 Features. Note: Documentation for previous COP8 devices, which in- ...
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Timers (Continued) FIGURE 15. Timer in PWM Mode If either used in High Speed PWM mode and an SBIT or RBIT instruction operates on any other bit of the PORT L Data Register, the PWM ...
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Timers (Continued) the external event occurs. The capture register eliminates the latency time, thereby allowing the applications program to retrieve the timer value stored in the capture register. In this mode, the timer Tx is constantly running at the ...
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Timers (Continued) Mode TxC3 TxC2 www.national.com TABLE 15. Timer Operating Modes Interrupt A TxC1 Description Source 1 PWM: TxA Toggle ...
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Timers (Continued) 12.4 TIMER T2 OPERATION IN IDLE MODE Timer T2 has a special mode that allows operated in IDLE mode. To use this mode, T2 must be configured as a high speed timer, by setting ...
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Power Saving Features Today, the proliferation of battery-operated applications has placed new demands on designers to drive power consump- tion down. Battery operated systems are not the only type of applications demanding low power. The power budget con- straints ...
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Power Saving Features (Continued) high speed clock. When this bit = 1, then the Core clock will be the low speed clock. Before switching this bit to either state, the appropriate clock should be turned on and stabilized. DCEN ...
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Power Saving Features (Continued) part of the oscillator closed loop.) When the IDLE Timer underflows, the clock signals are enabled on the chip, allow- ing program execution to proceed. Thus, the delay is equal to 256 instruction cycles. Note: ...
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Power Saving Features (Continued) IDLE mode. The NOP’s are placed either at the beginning of the IDLE Timer interrupt routine or immediately following the “enter IDLE mode” instruction. For more information on the IDLE Timer and its associated interrupt, ...
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Power Saving Features (Continued) The IDLE mode uses the on-chip IDLE Timer (Timer T0) to keep track of elapsed time in the IDLE state. The IDLE Timer runs continuously at the low speed clock rate, whether or not the ...
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Power Saving Features (Continued) 13.5.2 Low Speed Idle Mode In the IDLE mode, program execution stops and power consumption is reduced to a very low level as with the HALT mode. However, the low speed oscillator, IDLE Timer (Timer ...
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Power Saving Features (Continued) 13.6 MULTI-INPUT WAKE-UP The Multi-Input Wake-up feature is used to return (wake-up) the device from either the HALT or IDLE modes. Alternately Multi-Input Wake-up/Interrupt feature may also be used to generate edge ...
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USART (Continued) 14.1 USART CONTROL AND STATUS REGISTERS The operation of the USART is programmed through three registers: ENU, ENUR and ENUI. 14.2 DESCRIPTION OF USART REGISTER BITS ENU — USART CONTROL AND STATUS REGISTER (Ad- dress at 0BA) ...
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USART (Continued) XBIT9/PSEL0: Programs the ninth bit for transmission when the USART is operating with nine data bits per frame. For seven or eight data bits per frame, this bit in conjunction with PSEL1 selects parity. Read/Write, cleared on ...
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USART (Continued) 14.4 USART OPERATION The USART has two modes of operation: asynchronous mode and synchronous mode. 14.4.1 Asynchronous Mode This mode is selected by resetting the SSEL (in the ENUI register) bit to zero. The input frequency to ...
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USART (Continued) 14.6 USART INTERRUPTS The USART is capable of generating interrupts. Interrupts are generated on Receive Buffer Full and Transmit Buffer Empty. Both interrupts have individual interrupt vectors. Two bytes of program memory space are reserved for each ...
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USART (Continued) many ways to calculate the two divisor factors, but one particularly effective method would be to achieve a 1.8432 MHz frequency coming out of the first stage. The 1.8432 MHz prescaler output is then used to drive ...
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USART (Continued) Using the above equation can be calculated first 2)/(16 x 19200) = 32.552 Now 32.552 is divided by each Prescaler Factor (Table 20) to obtain ...
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A/D Converter This device contains a 7-channel, multiplexed input, succes- sive approximation, 10-bit Analog-to-Digital Converter with Programmable Gain Amplifier. One A/D channel is internally connected to the temperature sensor. The remaining six channels are connected to pins B2-B7 and ...
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A/D Converter (Continued) TABLE 22. A/D Converter Channel Selection when the Multiplexor Output is Disabled Select Bits ADCH3 ADCH2 Note 12: Only if the programmable ...
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A/D Converter (Continued) TABLE 23. A/D Converter Channel Selection when the Multiplexor Output is Enabled Select Bits ADCH3 ADCH2 ADCH1 ...
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A/D Converter (Continued) TABLE 26. ADRSTH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 TABLE 27. ADRSTL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 ...
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A/D Converter (Continued) 15.2.2 Programmable Gain Amplifier Offset Calibration The programmable gain amplifier has an offset that could be ± as high as 7 mV. When using this amplifier, a user may want to nullify this offset to obtain ...
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A/D Converter (Continued) 9. Wait 1.05 ms for the amplifier to settle. 10. Load 01h into ENAD to perform an A/D Conversion. 11. Store the result registers. 12. If the three most significant bits of the result are all ...
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A/D Converter (Continued) Source impedances greater than 3 kΩ on the analog input lines will adversely affect the internal RC charging time during input sampling. As shown in Figure 29, the analog switch to the Sample & Hold capacitor ...
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Stand-Alone Amplifier A stand-alone Amplifier, AMP1, is provided on Port B. It supports rail-to-rail inputs and outputs, and operates over the entire V and temperature range. This amplifier addition to the programmable gain amplifier in the ...
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Interrupts 18.1 INTRODUCTION The device supports fourteen vectored interrupts. Interrupt sources include Timer 1, Timer 2, Timer 3, Timer T0, Port L Wake-up, Software Trap, MICROWIRE/PLUS, USART and External Input. All interrupts force a branch to location 00FF Hex ...
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Interrupts (Continued) enabled; if the pending bit is already set, it will immediately trigger an interrupt. A maskable interrupt is active if its asso- ciated enable and pending bits are set. An interrupt is an asychronous event which may ...
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Interrupts (Continued) The default VIS interrupt vector can be useful for applica- tions in which time critical interrupts can occur during the servicing of another interrupt. Rather than restoring the pro- gram context ( etc.) and executing ...
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Interrupts (Continued) 18.4 NON-MASKABLE INTERRUPT 18.4.1 Pending Flag There is a pending flag bit associated with the non-maskable Software Trap interrupt, called STPND. This pending flag is not memory-mapped and cannot be accessed directly by the software. The pending ...
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Interrupts (Continued) STPND flag will have the wrong state. This will allow maskable interrupts to be acknowledged during the servicing of the first Software Trap. To avoid problems such as this, the user program should contain the Software Trap ...
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Interrupts (Continued) . SERVICE: RBIT,EXPND,PSW . . . RET I 18.5 PORT L INTERRUPTS Port L provides the user with an additional eight fully select- able, edge sensitive interrupts which are all vectored into the same service subroutine. The ...
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WATCHDOG/Clock Monitor TABLE 35. WATCHDOG Service Window Select WDSVR WDSVR Bit 7 Bit 19.1 CLOCK MONITOR The Clock Monitor aboard the device can be selected or ...
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WATCHDOG/Clock Monitor (Continued) • Following RESET, the WATCHDOG and CLOCK MONI- TOR are both enabled, with the WATCHDOG having the maximum service window selected. • The WATCHDOG service window and CLOCK MONI- TOR enable/disable option can only be changed ...
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MICROWIRE/PLUS 20.1 MICROWIRE/PLUS OPERATION Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS to start shifting the data. It gets reset when eight data bits have been shifted. The user may reset the BUSY bit by software ...
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MICROWIRE/PLUS mapped into the G6 configuration bit. The SKSEL flag will TABLE 39. MICROWIRE/PLUS Shift Clock Polarity and Sample/Shift Phase Port G SK Phase G6 (SKSEL) G5 Data Config. Bit Normal 0 Alternate 1 Alternate 0 Normal 1 FIGURE ...
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MICROWIRE/PLUS FIGURE 38. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High (Continued) 67 20006339 www.national.com ...
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Memory Map All RAM, ports and registers (except A and PC) are mapped into data memory address space. Address Contents S/ADD REG 0000 to 006F On-Chip RAM bytes (112 bytes) 0070 to 007F Unused RAM Address Space (Reads As ...
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Memory Map (Continued) Address Contents S/ADD REG xxED Timer T1 Autoload Register T1RA Upper Byte xxEE CNTRL Control Register xxEF PSW Register xxF0 to FB On-Chip RAM Mapped as Registers xxFC X Register xxFD SP Register xxFE B Register ...
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Instruction Set (Continued) or decremented after execution, allowing easy manipulation of memory blocks with software loops. In assembly lan- guage, the notation [B+], [B−], [X+], or [X−] specifies which register serves as the pointer, and whether the pointer is ...
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Instruction Set (Continued) Jump Indirect. In this 1-byte instruction, the lower byte of the jump address is obtained from a table stored in program memory, with the Accumulator serving as the low order byte of a pointer into program ...
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Instruction Set (Continued) 22.4.9 No-Operation Instruction The no-operation instruction does nothing, except to occupy space in the program memory and time in execution. No-Operation (NOP) Note: The VIS is a special case of the Indirect Transfer of Control addressing ...
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Instruction Set (Continued) 22.6 INSTRUCTION SET SUMMARY ADD A,Meml ADD ADC A,Meml ADD with Carry SUBC A,Meml Subtract with Carry AND A,Meml Logical AND ANDSZ A,Imm Logical AND Immed., Skip if Zero OR A,Meml Logical OR XOR A,Meml Logical ...
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Instruction Set (Continued) JSRL Addr. Jump SubRoutine Long JSR Addr. Jump SubRoutine JSRB Addr Jump SubRoutine Boot ROM JID Jump InDirect RET RETurn from subroutine RETSK RETurn and SKip RETI RETurn from Interrupt INTR Generate an Interrupt NOP No ...
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Instruction Set (Continued) Register Indirect [ (Note 17) 1 (Note 1/1 17)(Note 11) LD B,Imm LD B,Imm LD Mem,Imm 2/2 LD Reg,Imm IFEQ MD,Imm > Note 17: = Memory location addressed ...
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Nibble Lower 76 ...
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Development Support Vendor Home Office K and K Kaergaardsvej 42 DK-8355 Development ApS Solbjerg Denmark Fax: +45-8692-8500 National 2900 Semiconductor Dr. Semiconductor Santa Clara, CA 95051 USA Tel: 1-800-272-9959 Fax: 1-800-737-7018 SofTec Microsystems Via Roma, 1 33082 Azzano Decimo ...
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... Physical Dimensions meters) unless otherwise noted www.national.com inches (milli- Molded SO Wide Body Package (MW) Order Number COP8AME9EMW8 NS Package Number M28B Molded Dual-In-Line Package (N) Order Number COP8AME9ENA8 NS Package Number N28B 82 ...
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LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support ...