COP8ACC720M9-RE NSC [National Semiconductor], COP8ACC720M9-RE Datasheet - Page 17

• Manufacturer Part Number: COP8ACC720M9-RE
• Description: 8-Bit CMOS OTP Microcontroller with 16k Memory and High Resolution A/D
• Manufacturer: NSC [National Semiconductor]

Timers
Capture Overflow interrupt and Capture Pending interrupt
share the same interrupt vector.
CAPCNTL Register (Address (X’CE)
The CAPCNTL register contains the following bits:
Reserved These bits are reserved and must be zero.
CAPMOD Reset Time.
CAPRUN Capture Timer Run. Setting this bit to one will
CAPOVL
CAPPND Capture pending.
CAPIEN
Power Save Modes
The device offers the user two power save modes of opera-
tion: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board oscil-
lator circuitry and timer T0 are active but all other microcon-
troller activities are stopped. In either mode, all on-board
RAM, registers, I/O states, and timers (with the exception of
T0) are unaltered.
HALT MODE
The device can be placed in the HALT mode by writing a “1”
to the HALT flag (G7 data bit). All microcontroller activities,
including the clock and timers, are stopped. The WATCH-
DOG logic on the device is disabled during the HALT mode.
However, the clock monitor circuitry, if enabled, remains ac-
tive and will cause the WATCHDOG output pin (WDOUT) to
go low. If the HALT mode is used and the user does not want
to activate the WDOUT pin, the Clock Monitor should be dis-
abled after the device comes out of reset (resetting the Clock
Monitor control bit with the first write to the WDSVR register).
In the HALT mode, the power requirements of the device are
minimal and the applied voltage (V
V
The device supports three different ways of exiting the HALT
mode. The first method of exiting the HALT mode is with the
Multi-Input Wakeup feature on the Port L.
The second method is with a low to high transition on the
CKO (G7) pin. This method precludes the use of the crystal
clock configuration (since CKO becomes a dedicated out-
put), and so may only be used with an RC clock configura-
tion. The third method of exiting the HALT mode is by pulling
the RESET pin low.
Reserved
r
Bit 7-5
(V
r
= 2.0V) without altering the state of the machine.
CAPMOD
Capture Timer Overflow. Gets set to “1” upon
0: reset timer to “0” when CAPRUN bit gets set
1: DO NOT reset timer to “0” when CAPRUN bit
gets set.
start the capture timer. This bit gets automatically
reset to “0” when a capture events occurs. Writ-
ing a “0” by software will also reset the bit and
stop the timer.
timer overflow. Has to be reset by user’s soft-
ware. If CAPIEN = 1 an interrupt is generated.
Gets automatically set when a capture event oc-
curs. If CAPIEN = 1 an interrupt is generated.
Has to be reset by the user’s software.
Capture Interrupt enable,
1 = enable interrupts, 0 = disable interrupts
(Continued)
Bit 4
CAPRUN
CAPOVL
CC
) may be decreased to
CAPPND
CAPIEN
Bit 0
17
Since a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full ampli-
tude and frequency stability. The IDLE timer is used to gen-
erate a fixed delay to ensure that the oscillator has indeed
stabilized before allowing instruction execution. In this case,
upon detecting a valid Wakeup signal, only the oscillator cir-
cuitry is enabled. The IDLE timer is loaded with a value of
256 and is clocked with the t
clock is derived by dividing the oscillator clock down by a fac-
tor of 10. The Schmitt trigger following the CKI inverter on
the chip ensures that the IDLE timer is clocked only when the
oscillator has a sufficiently large amplitude to meet the
Schmitt trigger specifications. This Schmitt trigger is not part
of the oscillator closed loop. The startup timeout from the
IDLE timer enables the clock signals to be routed to the rest
of the chip.
If an RC clock option is being used, the fixed delay is intro-
duced optionally. A control bit, CLKDLY, mapped as configu-
ration bit G7, controls whether the delay is to be introduced
or not. The delay is included if CLKDLY is set, and excluded
if CLKDLY is reset. The CLKDLY bit is cleared on reset.
The device has two mask options associated with the HALT
mode. The first mask option enables the HALT mode feature,
while the second mask option disables the HALT mode. With
the HALT mode enable mask option, the device will enter
and exit the HALT mode as described above. With the HALT
disable mask option, the device cannot be placed in the
HALT mode (writing a “1” to the HALT flag will have no effect,
the HALT flag will remain “0”).
IDLE MODE
In the IDLE mode, program execution stops and power con-
sumption is reduced to a very low level as with the HALT
mode. However, the on-board oscillator, IDLE Timer (Timer
T0), and Clock Monitor continue to operate, allowing real
time to be maintained. The device remains idle for a selected
amount of time up to 65,536 instruction cycles, or 65.536 mil-
liseconds with a 1 MHz instruction clock frequency, and then
automatically exits the IDLE mode and returns to normal pro-
gram execution.
The device is placed in the IDLE mode under software con-
trol by setting the IDLE bit (bit 6 of the Port G data register).
The IDLE timer window is selectable from one of five values,
4k, 8k, 16k, 32k or 64k instruction cycles. Selection of this
value is made through the ITMR register.
The IDLE mode uses the on-chip IDLE Timer (Timer T0) to
keep track of elapsed time in the IDLE state. The IDLE timer
runs continuously at the instruction clock rate, whether or not
the device is in the IDLE mode. Each time the bit of the timer
associated with the selected window toggles, the T0PND bit
is set, an interrupt is generated (if enabled), and the device
exits the IDLE mode if in that mode. If the IDLE timer inter-
rupt is enabled, the interrupt is serviced before execution of
the main program resumes. (However, the instruction which
was started as the part entered the IDLE mode is completed
before the interrupt is serviced. This instruction should be a
NOP which should follow the enter IDLE instruction.) The
user must reset the IDLE timer pending flag (T0PND) before
entering the IDLE mode.
As with the HALT mode, this device can also be returned to
normal operation with a reset, or with a Multi-Input Wakeup
input. Upon reset the ITMR register is cleared and the ITMR
register selects the 4,096 instruction cycle tap of the Idle
Timer.
C
instruction cycle clock. The t
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