COP87L84FH NSC [National Semiconductor], COP87L84FH Datasheet
COP87L84FH
Related parts for COP87L84FH
COP87L84FH Summary of contents
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... ROM design. Lower cost pin and software compatible 12k ROM versions are available (COP888FH), as well as a range of COP8 software and hardware development tools. Device Memory (bytes) COP87L84FH 16k OTP EPROM COP87L88FH 16k OTP EPROM Key Features n Hardware Multiply/Divide Functions ...
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Block Diagram www.national.com FIGURE 1. COP87L88FH Block Diagram 2 DS101135-1 ...
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... Connection Diagrams Plastic Chip Carrier Top View Order Number COP87L88FHV-XE/TE See NS Plastic Chip Package Number V44A Order Number COP87L84FHM-XE/TE, or COP87L84FHN-XE/TE See NS Molded Package Number M28B or N28B Note: -X Crystal Oscillator -T External Clock -E Halt Mode Enable Dual-In-Line Package DS101135-2 Top View Order ...
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Connection Diagrams (Continued) Pinouts for 28-, 40- and 44-Pin Packages Port Type L0 I/O MIWU L1 I/O MIWU L2 I/O MIWU L3 I/O MIWU L4 I/O MIWU L5 I/O MIWU L6 I/O MIWU L7 I/O MIWU G0 I/O INT G1 ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin −0. Electrical Characteristics −40˚C T +85˚C unless ...
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DC Electrical Characteristics −40˚C T +85˚C unless otherwise specified A Parameter Input Capacitance (Note 6) Load Capacitance on D2 (Note 6) AC Electrical Characteristics −40˚C T +85˚C unless otherwise specified A Parameter Instruction Cycle Time ( Crystal Resonator ...
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Comparators AC and DC Characteristics = 5V, −40˚ +85˚ Parameter High Level Output Current DC Supply Current Per Comparator (When Enabled) Response Time (Continued) Conditions Min = 4.6V V 1.6 OH 100 mV Overdrive, 100 pF ...
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Pin Descriptions V and GND are the power supply pins. All V CC pins must be connected. CKI is the clock input. This can come from an R/C generated oscillator crystal oscillator (in conjunction with CKO). See Oscillator ...
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Pin Descriptions (Continued) The Port I has the following alternate features. I6 COMP2OUT (Comparator 2 Output) I5 COMP2+IN (Comparator 2 Positive Input) I4 COMP2−IN (Comparator 2 Negative Input) I3 COMP1OUT (Comparator 1 Output) I2 COMP1+IN (Comparator 1 Positive Input) I1 ...
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Data Memory Segment RAM Extension (Continued) Figure 5 illustrates how the S register data memory exten- sion is used in extending the lower half of the base address range ( hex) into 256 data segments of 128 bytes ...
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Reset (Continued) DS101135-8 > Power Supply Rise Time FIGURE 6. Recommended Reset Circuit Oscillator Circuits The chip can be driven by a clock input on the CKI input pin which can be between DC and 10 MHz. ...
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Control Registers CNTRL Register (Address X'00EE) T1C3 T1C2 T1C1 T1C0 MSEL Bit 7 The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits: T1C3 Timer T1 mode control bit T1C2 Timer T1 mode control bit T1C1 Timer T1 mode ...
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Timers The device contains a very versatile set of timers (T0, T1, T2, T3). All timers and associated autoreload/capture regis- ters power up containing random data. TIMER T0 (IDLE TIMER) The device supports applications that require maintaining real time and ...
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Timers (Continued) FIGURE 9. Timer in External Event Counter Mode Mode 3. Input Capture Mode The device can precisely measure external frequencies or time external events by placing the timer block, Tx, in the in- put capture mode. In this ...
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Timers (Continued) Mode TxC3 TxC2 TxC1 Power Save Modes The device offers the user two power save modes of opera- tion: HALT and IDLE. In the HALT ...
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Power Save Modes (Continued) Alternatively, the user can enter the IDLE mode with the IDLE Timer T0 interrupt disabled. In this case, the device will resume normal operation with the instruction immediately following the “Enter IDLE Mode” instruction. Note: It ...
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Multi-Input Wakeup (Continued) both enabled and pending. Consequently, the user has the responsibility of clearing the pending flags before attempting to enter the HALT mode. WKEN, WKPND and WKEDG are all read/write registers, and are cleared at reset. PORT L ...
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USART (Continued) USART CONTROL AND STATUS REGISTERS The operation of the USART is programmed through three registers: ENU, ENUR and ENUI. DESCRIPTION OF USART REGISTER BITS ENU-USART Control and Status Register (Address at 0BA) PEN PSEL1 XBIT9/ CHL1 CHL0 PSEL0 ...
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USART (Continued) ETI: This bit enables/disables interrupt from the transmitter section. Read/Write, cleared on reset. ETI = 0 Interrupt from the transmitter is disabled. ETI = 1 Interrupt from the transmitter is enabled. Associated I/O Pins Data is transmitted on ...
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USART Operation (Continued) USART INTERRUPTS The USART is capable of generating interrupts. Interrupts are generated on Receive Buffer Full and Transmit Buffer Empty. Both interrupts have individual interrupt vectors. Two bytes of program memory space are reserved for each inter- ...
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Baud Clock Generation (Continued) FIGURE 14. USART BAUD Clock Generation FIGURE 15. USART BAUD Clock Divisor Registers TABLE 3. Prescaler Factors Prescaler Prescaler Select Factor 00000 NO CLOCK 00001 1 00010 1.5 00011 2 00100 2.5 00101 3 00110 3.5 ...
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Baud Clock Generation The divide performed because in the asynchronous mode, the input frequency to the USART is 16 times the baud rate. The equation to calculate baud rates is given be- low. The actual Baud Rate ...
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Comparators (Continued) should also be disabled before entering either the HALT or IDLE modes in order to save power. The configuration of the CMPSL register is as follows: CMPSL REGISTER (ADDRESS X’00B7) Rsvd CMP20E CMP2RD CMP2EN CMP10E CMP1RD Bit 7 ...
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Multiply/Divide (Continued) Register Name Multiplication Assignment (Address) Before Operation MDR1 (xx98) Unused MDR2 (xx99) Multiplier MDR3 (xx9A) MDR4 (xx9B) Low Byte of Multiplicand MDR5 (xx9C) High Byte of Multiplicand Interrupts Introduction Each device supports thirteen vectored interrupts. Interrupt sources include ...
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Interrupts (Continued) MASKABLE INTERRUPTS All interrupts other than the Software Trap are maskable. Each maskable interrupt has an associated enable bit and pending flag bit. The pending bit is set to 1 when the interrupt condition occurs. The state of ...
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Interrupts (Continued) ample, if the Software Trap routine is located at 0310 Hex, then the vector location 0yFE and -0yFF should contain the data 03 and 10 Hex, respectively. When a Software Trap in- terrupt occurs and the VIS instruction ...
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Interrupts (Continued) Figure 17 illustrates the different steps performed by the VIS instruction. Figure 18 shows a flowchart for the VIS instruc- tion. The non-maskable interrupt pending flag is cleared by the RPND (Reset Non-Maskable Pending Bit) instruction (under certain ...
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Interrupts (Continued) Programming Example: External Interrupt PSW =00EF CNTRL =00EE RBIT 0,PORTGC RBIT 0,PORTGD SBIT IEDG, CNTRL SBIT EXEN, PSW SBIT GIE, PSW WAIT: JP WAIT . . . .=0FF VIS . . . .=01FA .ADDRW SERVICE . . INT_EXIT: ...
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Interrupts (Continued) NON-MASKABLE INTERRUPT Pending Flag There is a pending flag bit associated with the non-maskable interrupt, called STPND. This pending flag is not memory- mapped and cannot be accessed directly by the software. The pending flag is reset to ...
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WATCHDOG The device contains a WATCHDOG and clock monitor. The WATCHDOG is designed to detect the user program getting stuck in infinite loops resulting in loss of program control or “runaway” programs. The Clock Monitor is used to detect the ...
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WATCHDOG Operation (Continued) • The initial WATCHDOG service must match the key data value in the WATCHDOG Service register WDSVR in or- der to avoid a WATCHDOG error. • Subsequent WATCHDOG services must match all three data fields in WDSVR ...
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MICROWIRE/PLUS (Continued) Key Window Data Data Match Match Don’t Care Mismatch Mismatch Don’t Care Don’t Care Don’t Care TABLE 10. MICROWIRE/PLUS Master Mode Clock Select SL1 SL0 ...
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MICROWIRE/PLUS (Continued) FIGURE 20. MICROWIRE/PLUS Application 33 DS101135-23 www.national.com ...
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Memory Map All RAM, ports and registers (except A and PC) are mapped into data memory address space. Address Contents S/ADD REG 0000 to 006F On-Chip RAM bytes (112 bytes) 0070 to 007F Unused RAM Address Space (Reads As All ...
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Addressing Modes There are ten addressing modes, six for operand addressing and four for transfer of control. OPERAND ADDRESSING MODES Register Indirect This is the “normal” addressing mode. The operand is the data memory addressed by the B pointer or ...
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Instruction Set (Continued) INSTRUCTION SET ADD A,Meml ADD ADC A,Meml ADD with Carry SUBC A,Meml Subtract with Carry AND A,Meml Logical AND ANDSZ A,Imm Logical AND Immed., Skip if Zero OR A,Meml Logical OR XOR A,Meml Logical EXclusive OR IFEQ ...
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Instruction Set (Continued) JSRL Addr. Jump SubRoutine Long JSR Addr Jump SubRoutine JID Jump InDirect RET RETurn from subroutine RETSK RETurn and SKip RETI RETurn from Interrupt INTR Generate an Interrupt NOP No OPeration [SP] PL, [SP−1] PU,SP− ...
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Instruction Execution Time Most instructions are single byte (with immediate addressing mode instructions taking two bytes). Most single byte instructions take one cycle time to execute. Skipped instructions require x number of cycles to be skipped, where x equals the ...
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Instruction Execution Time (Continued) 3–0 Bits 39 www.national.com ...
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Development Tools Support OVERVIEW National is engaged with an international community of inde- pendent 3rd party vendors who provide hardware and soft- ware development tool support. Through National’s interac- tion and guidance, these tools cooperate to form a choice of ...
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... COP8-NSEVAL COP8-NSASM COP8-NSASM COP8-MLSIM COP8-MLSIM COP8-NSDEV COP8-NSDEV COP8-EPU Not available for this device COP8-DM Contact MetaLink Development COP87L84FH Devices COP87L88FH IM-COP8 Contact MetaLink MetaLink COP8-EPU Not available for this device COP8-DM DM4-COP8-888FH (10 MHz), plus PS-10, plus DM-COP8/xxx (ie. 40D) IM-COP8 IM-COP8-AD-464 (-220) ...
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Development Tools Support WHERE TO GET TOOLS Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors. Vendor Home Office Aisys U.S.A.: Santa Clara, CA 1-408-327-8820 fax: 1-408-327-8830 Byte Craft ...
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Physical Dimensions inches (millimeters) unless otherwise noted COP884FH-XXX/M or COP984FH-XXX/M COP884FH-XXX/N or COP984FH-XXX/N Molded SO Wide Body Package (M) Order Number COP684FH-XXX/M, NS Package Number M28B Molded Dual-In-Line Package (N) Order Number COP684FH-XXX/N, NS Package Number N28B 43 www.national.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) www.national.com Molded Dual-In-Line Package (N) Order Number COP688FH-XXX/N, COP888FH-XXX/N or COP988FH-XXX/N NS Package Number N40A Plastic Leaded Chip Carrier (V) Order Number COP688FH-XXX/V, COP888FH-XXX/V or COP988FH-XXX/V NS Package Number V44A 44 ...
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LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support ...