COP87L84EK NSC [National Semiconductor], COP87L84EK Datasheet - Page 12

• Manufacturer Part Number: COP87L84EK
• Description: 8-Bit CMOS OTP Microcontrollers with 8k or 32k Memory, Comparator, and Single-slope A/D Capability
• Manufacturer: NSC [National Semiconductor]

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Data Memory Segment RAM
Extension
*Reads as all ones.
Reset
The RESET input when pulled low initializes the microcon-
troller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for ports L, G and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is dedi-
cated as the WATCHDOG and/or Clock Monitor error output
pin. Port D is set high. The PC, PSW, ICNTRL, CNTRL,
T2CNTRL and T3CNTRL control registers are cleared. The
Comparator Select Register is cleared. The S register is ini-
tialized to zero. The Multi-Input Wakeup registers WKEN and
WKEDG are cleared. Wakeup register WKPND is unknown.
The stack pointer, SP, is initialized to 6F hex.
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are in-
hibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k t
being initialized high will cause a Clock Monitor error follow-
ing reset if the clock has not reached the minimum specified
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error
output will continue until 16 t
the clock frequency reaching the minimum specified value,
at which time the G1 output will enter the TRI-STATE mode.
The external RC network shown in Figure 6 should be used
to ensure that the RESET pin is held low until the power sup-
ply to the chip stabilizes.
FIGURE 5. RAM Organization
(Continued)
C
clock cycles. The Clock Monitor bit
C
–32 t
C
clock cycles following
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12
RC
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input fre-
quency is divided down by 10 to produce the instruction
cycle clock (1/t
Note: External clocks with frequencies above about 4 MHz require the user
Figure 7 shows the Crystal and R/C oscillator diagrams.
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop crys-
tal (or resonator) controlled oscillator.
Table 1 shows the component values required for various
standard crystal values.
R/C OSCILLATOR
By selecting CKI as a single pin oscillator input, a single pin
R/C oscillator circuit can be connected to it. CKO is available
as a general purpose input, and/or HALT restart input.
Note: Use of the R/C oscillator option will result in higher electromagnetic
Table 2 shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
>
FIGURE 7. Crystal and R/C Oscillator Diagrams
to drive the CKO (G7) pin with a signal 180 degrees out of phase with
CKI.
emissions.
5 x Power Supply Rise Time
FIGURE 6. Recommended Reset Circuit
c
).
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