R5F21133DFP RENESAS [Renesas Technology Corp], R5F21133DFP Datasheet - Page 220

• Manufacturer Part Number: R5F21133DFP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY/R8C/Tiny SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

1.20 Jan.27.2006
Rev.
Date
REVISION HISTORY
Page
102
107
108
120
125
135
138
111
112
113
10
12
13
15
18
29
32
35
38
42
46
51
59
71
74
88
11
9
Table 4.2 SFR Information(2) NOTES:1 revised
Table 4.3 SFR Information(3);
0081
0082
0083
0085
0086
0087
008C
NOTES:1, 2 revised
Table 4.4 SFR Information(4) NOTES:1 revised
Figure 5.2 Reset Sequence; “72cycles”
5.1.3 Power-on Reset Function revised
6 Clock Generation Circuit;
“(oscillation stop detect function)”
Table 6.1 Clock Generation Circuit Specifications NOTES: 2 deleted
Figure 6.3 OCD Register NOTES: 3 partly deleted
6.2.1 Low-Speed On-Chip Oscillator Clock;
“The application products ... to accommodate the frequency range.”
“The application products ... for the frequency change.” revised
Table 6.2 Setting Clock Related Bit and Modes CM13 added
6.5.1 How to Use Oscillation Stop Detection Function:
“This function cannot ... is below 2 MHz.” added
Table 9.1 Bus Cycles for Access Space, Table 9.2 Access Unit and Bus Operation;
“SFR”
ROM/RAM”
Table 10.2 Relocatable Vector Tables; “A/D”
Figure 10.9 Interrupts Priority Select Circuit NOTES: 1 deleted
Figure 12.1 Timer X Block Diagram; “Peripheral data bus”
Table 12.3 Pulse Output Mode Specifications NOTES: 1 added
Figure 12.18 Timer Z Block Diagram; “Peripheral data bus”
Figure 12.30 CMP Waveform Output Unit revised
Table 12.14 Output Compare Mode Specifications NOTES: 2 revised
Figure 12.34 Operation Example of Timer C in Output Compare Mode revised
Figure 13.3 U0TB to U1TB Registers, U0RB and U1RB Registers, and U0BRG and
U1BRG Registers;
UARTi transmit buffer register (i=0, 1) revised
UARTi bit rate register (i=0, 1); NOTES: 3 added
Figure 13.4 U0MR to U1MR Registers and U0C0 and U1C0 Registers;
UARTi transmit/receive control register 0 (i=0, 1); NOTES: 1 added
Figure 13.5 U0C1 and U1C1 Registers and UCON Register;
UART transmit/receive control register 2; NOTES: 2 added
Table 13.5 Registers to Be Used and Settings in UART Mode;
UiBRG: “–”
Figure 14.1 A/D Converter Block Diagram “Vref”
14.7 Output Impedance of Sensor under A/D Conversion added
Figure 15.1 Programmable I/O Ports (1); NOTES: 1 added
3 Memory, Figure 3.1 Memory Map;
“Program area”
Table 4.1 SFR Information(1) NOTES:1 revised
16
16
16
16
16
16
16
: “Prescaler Y”
: “Timer Y Secondary”
: “Timer Y Primary”
: “Prescaler Z”
: “Timer Z Secondary”
: “Timer Z Primary”
: “Prescaler X”
“SFR, Data flash”,
“0 to 7” revised
“Program ROM/RAM” revised
“Program ROM”, “Data area”
C-4
“Prescaler Y Register”
“Prescaler Z Register”
“Prescaler X Register” revised
“Timer Z Primary Register”
“Timer Y Primary Register”
Description
R8C/13 Group Hardware Manual
“Timer Y Secondary Register”
“Timer Z Secondary Register”
Summary
“(oscillation stop detection function)” revised
“64cycles” revised
“A/D Conversion” revised
“Vcom” revised
“Data flash” revised
“Data bus” revised
“Data bus” revised