MC908QL4 FREESCALE [Freescale Semiconductor, Inc], MC908QL4 Datasheet - Page 145

• Manufacturer Part Number: MC908QL4
• Description: M68HC08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor
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No Interrupts Pending
This value indicates that all pending interrupt sources have been serviced. In polling mode, the
SLCSV is read and interrupts serviced until this value reads back 0. This source will not generate
an interrupt of the CPU, regardless of state of SLCIE.
No Bus Activity (LIN specified error)
The No-Bus-Activity condition occurs if no valid SYNCH BREAK FIELD or BYTE FIELD was
received for more than 2
example, with 6.4 MHz SLIC clock frequency, a No-Bus-Activity interrupt will occur about 1.31
seconds after the bus begins to idle.
TX Message Buffer Empty — Checksum Transmitted
When the entire LIN message frame has been transmitted successfully, complete with the
appropriately selected checksum byte, this interrupt source is asserted. This source is used for all
standard LIN message frames and the final set of bytes with extended LIN message frames.
TX Message Buffer Empty
This interrupt source indicates that all 8 bytes in the LIN message buffer have been transmitted
with no checksum appended. This source is used for intermediate sets of 8 bytes in extended LIN
message frames.
RX Message Buffer Full — Checksum OK
When the entire LIN message frame has been received successfully, complete with the
appropriately selected checksum byte, and the checksum calculates correctly, this interrupt source
is asserted. This source is used for all standard LIN message frames and the final set of bytes with
extended LIN message frames. To clear this source, SLCD0 must be read first.
RX Data Buffer Full — No Errors
This interrupt source indicates that 8 bytes have been received with no checksum byte and are
waiting in the LIN message buffer. This source is used for intermediate sets of 8 bytes in extended
LIN message frames. To clear this source, SLCD0 must be read first.
Bit Error
A unit that is sending a bit on the bus also monitors the bus. A BIT_ERROR must be detected at
that bit time, when the bit value that is monitored is different from the bit value that is sent. The
SLIC will terminate the data transmission upon detection of a bit error, according to the LIN
SLCSV
$1C
$2C
$3C
$20
$24
$28
$30
$34
$38
Table 14-2. Interrupt Sources Summary (BTM = 0) (Continued)
I3
0
1
1
1
1
1
1
1
1
I2
1
0
0
0
0
1
1
1
1
23
SLIC clock counts since the reception of the last valid message. For
I1
1
0
0
1
1
0
0
1
1
MC68HC908QL4 Data Sheet, Rev. 7
I0
1
0
1
0
1
0
1
0
1
Identifier Received Successfully
Inconsistent-Synch-Field-Error
Receiver Buffer Overrun
Identifier Parity Error
Byte Framing Error
Interrupt Source
Checksum Error
Reserved
Reserved
Wakeup
15 (Highest)
Priority
11
12
14
10
13
7
8
9
Registers
145