MC908GR16ACFA FREESCALE [Freescale Semiconductor, Inc], MC908GR16ACFA Datasheet - Page 196

• Manufacturer Part Number: MC908GR16ACFA
• Description: M68HC08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Serial Peripheral Interface (SPI) Module
input (SS) is low, so that only the selected slave drives to the master. The SS pin of the master is not
shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as
general-purpose I/O not affecting the SPI. (See
SPSCK edge is the MSB capture strobe. Therefore, the slave must begin driving its data before the first
SPSCK edge, and a falling edge on the SS pin is used to start the slave data transmission. The slave’s
SS pin must be toggled back to high and then low again between each byte transmitted as shown in
Figure
When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission. This
causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from the transmit data register.
Therefore, the SPI data register of the slave must be loaded with transmit data before the falling edge of
SS. Any data written after the falling edge is stored in the transmit data register and transferred to the shift
register after the current transmission.
16.4.3 Transmission Format When CPHA = 1
Figure 16-7
replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing
diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins
are directly connected between the master and the slave. The MISO signal is the output from the slave,
and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The
slave SPI drives its MISO output only when its slave select input (SS) is low, so that only the selected
slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS
196
16-6.
shows an SPI transmission in which CPHA = 1. The figure should not be used as a
CAPTURE STROBE
FOR REFERENCE
SPSCK; CPOL = 0
MASTER SS
SPSCK; CPOL =1
MISO/MOSI
SPSCK CYCLE #
FROM MASTER
SLAVE SS
SLAVE SS
CPHA = 0
CPHA = 1
SS; TO SLAVE
FROM SLAVE
MOSI
MISO
Figure 16-5. Transmission Format (CPHA = 0)
MSB
MC68HC908GR16A Data Sheet, Rev. 1.0
MSB
BYTE 1
Figure 16-6. CPHA/SS Timing
1
BIT 6
BIT 6
2
16.6.2 Mode Fault
BIT 5
BIT 5
3
BYTE 2
BIT 4
BIT 4
4
BIT 3
BIT 3
5
Error.) When CPHA = 0, the first
BIT 2
BIT 2
6
BYTE 3
BIT 1
BIT 1
7
LSB
LSB
8
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