Z8F1602 ZILOG [Zilog, Inc.], Z8F1602 Datasheet - Page 143
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Z8F1602
Manufacturer Part Number
Z8F1602
Description
Z8 Encore Microcontrollers with Flash Memory and 10-Bit A/D Converter
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.Z8F1602.pdf
(246 pages)
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Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
®
Z8 Encore!
125
1 = DMAx is enabled and initiates a data transfer upon receipt of a request from the trigger
source.
DLE—DMAx Loop Enable
0 = DMAx reloads the original Start Address and is then disabled after the End Address
data is transferred.
1 = DMAx, after the End Address data is transferred, reloads the original Start Address
and continues operating.
DDIR—DMAx Data Transfer Direction
0 = Register File → on-chip peripheral control register.
1 = on-chip peripheral control register → Register File.
IRQEN—DMAx Interrupt Enable
0 = DMAx does not generate any interrupts.
1 = DMAx generates an interrupt when the End Address data is transferred.
WSEL—Word Select
0 = DMAx transfers a single byte per request.
1 = DMAx transfers a two-byte word per request. The address for the on-chip peripheral
control register must be an even address.
RSS—Request Trigger Source Select
The Request Trigger Source Select field determines the peripheral that can initiate a DMA
request transfer. The corresponding interrupts do not need to be enabled within the Inter-
rupt Controller to initiate a DMA transfer. However, if the Request Trigger Source can
enable or disable the interrupt request sent to the Interrupt Controller, the interrupt request
must be enabled within the Request Trigger Source block.
000 = Timer 0.
001 = Timer 1.
010 = Timer 2.
011 = Timer 3.
100 = DMA0 Control register: UART0 Received Data register contains valid data. DMA1
Control register: UART0 Transmit Data register empty.
101 = DMA0 Control register: UART1 Received Data register contains valid data. DMA1
Control register: UART1 Transmit Data register empty.
2
2
110 = DMA0 Control register: I
C Receiver Interrupt. DMA1 Control register: I
C Trans-
mitter Interrupt register empty.
111 = Reserved.
DMAx I/O Address Register
The DMAx I/O Address register contains the low byte of the on-chip peripheral address
for data transfer. The full 12-bit Register File address is given by {FH, DMAx_IO[7:0]}.
PS017610-0404
Direct Memory Access Controller
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