AT91SAM7XC128 ATMEL [ATMEL Corporation], AT91SAM7XC128 Datasheet
AT91SAM7XC128
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AT91SAM7XC128 Summary of contents
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... Internal High-speed Flash – 256 Kbytes (AT91SAM7XC256) Organized in 1024 Pages of 256 Bytes – 128 Kbytes (AT91SAM7XC128) Organized in 512 Pages of 256 Bytes – Single Cycle Access MHz in Worst Case Conditions – Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed – ...
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Seventeen Peripheral DMA Controller (PDC) Channels • One Advanced Encryption System (AES) – 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications – Buffer Encryption/Decryption Capabilities with PDC • One Triple Data Encryption System (TDES) – Two-key or Three-key ...
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... AT91SAM7XC256/128 is a powerful device that provides a flexible, cost-effective solution to many embedded control applications requiring secure communication over, for example, Ether- net, CAN wired and Zigbee wireless networks. 2. Configuration Summary of the AT91SAM7XC256 and AT91SAM7XC128 The AT91SAM7XC256 and AT91SAM7XC128 differ only in memory sizes. rizes the configurations of the two devices. Table 2-1. Device ...
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AT91SAM7XC256/128 Block Diagram Figure 3-1. JTAGSEL IRQ0-IRQ1 PCK0-PCK3 VDDCORE VDDFLASH VDDCORE SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK ADTRG ADVREF AT91SAM7XC256/128 Preliminary 4 AT91SAM7XC256/128 Block Diagram TDI TDO ICE JTAG TMS SCAN ...
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Signal Description Table 4-1. Signal Description List Signal Name Function Voltage Regulator and ADC Power VDDIN Supply Input VDDOUT Voltage Regulator Output VDDFLASH Flash and USB Power Supply VDDIO I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL ...
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Table 4-1. Signal Description List (Continued) Signal Name Function DDM USB Device Port Data - DDP USB Device Port Data + SCK0 - SCK1 Serial Clock TXD0 - TXD1 Transmit Data RXD0 - RXD1 Receive Data RTS0 - RTS1 Request ...
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Table 4-1. Signal Description List (Continued) Signal Name Function AD0-AD3 Analog Inputs AD4-AD7 Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference PGMEN0-PGMEN1 Programming Enabling PGMM0-PGMM3 Programming Mode PGMD0-PGMD15 Programming Data PGMRDY Programming Ready PGMNVALID Data Direction PGMNOE Programming Read PGMCK ...
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Package The AT91SAM7XC256/128 is available in 100-lead LQFP package. 5.1 100-lead LQFP Mechanical Overview Figure 5-1 tion is given in the Mechanical Characteristics section of the full datasheet. Figure 5-1. 5.2 AT91SAM7XC256/128 Pinout Table 5-1. Pinout in 100-lead TQFP ...
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Power Considerations 6.1 Power Supplies The AT91SAM7XC256/128 has six types of power supply pins and integrates a voltage regula- tor, allowing the device to be supplied with only one voltage. The six power supply pin types are: • VDDIN ...
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Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 ...
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I/O Lines Considerations 7.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs and are not 5-V tolerant. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven VDDIO, ...
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I/O Lines Current Drawing The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive permanently. The remaining I/O lines can draw only 8 mA. However, the total current ...
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Processor and Architecture 8.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann architecture – Runs MHz, providing 0.9 MIPS/MHz • Two instruction sets – ARM – Thumb • Three-stage pipeline architecture – Instruction ...
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Embedded Flash Controller – Embedded Flash interface three programmable wait states – Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required – Key-protected program, erase and lock/unlock sequencer – Single command for erasing, programming and ...
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... Protection Mode to secure contents of the Flash • 64 Kbytes of Fast SRAM – Single-cycle access at full speed 9.2 AT91SAM7XC128 • 128 Kbytes of Flash Memory – 512 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – ...
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... Internal Flash • The AT91SAM7XC256 features one bank of 256 Kbytes of Flash • The AT91SAM7XC128 features one bank of 128 Kbytes of Flash. At any time, the Flash is mapped to address 0x0010 0000 also accessible at address 0x0 after the reset and before the Remap Command. ...
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... Flash Overview • The Flash of the AT91SAM7XC256 is organized in 1024 pages of 256 bytes. It reads as 65,536 32-bit words. • The Flash of the AT91SAM7XC128 is organized in 512 pages of 256 bytes. It reads as 32,768 32-bit words. The Flash contains a 256-byte write buffer, accessible through a 32-bit interface. The Flash benefits from the integration of a power reset cell and from the brownout detector. ...
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... AT91SAM7XC128 The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7XC128 contains 8 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes locked-region’s erase or program command occurs, the command is aborted and the EFC trigs an interrupt. The 8 NVM bits are software programmable through the EFC User Interface. The command “ ...
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GPNVM Bit 0 is used as a brownout detector enable bit. Setting the GPNVM Bit 0 enables the BOD, clearing it disables the BOD. Asserting ERASE clears the GPNVM Bit 0 and thus disables the brownout detector by default. ...
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System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. Figure 10-1. System Controller Block Diagram NRST XIN XOUT PLLRC PA0-PA30 PB0-PB30 AT91SAM7XC256/128 Preliminary 20 System Controller irq0-irq1 Advanced fiq ...
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System Controller Mapping The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF. Figure 10-2 figuration user interface is also mapped within this address space. Figure 10-2. ...
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Reset Controller • Based on one power-on reset cell and one brownout detector • Status of the last reset, either Power-up Reset, Software Reset, User Reset, Watchdog Reset, Brownout Reset • Controls the internal resets and the NRST pin ...
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Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: • RC Oscillator ranges between 22 KHz and 42 KHz • Main Oscillator frequency ranges between 3 and 20 ...
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Power Management Controller The Power Management Controller uses the Clock Generator outputs to provide: • the Processor Clock PCK • the Master Clock MCK • the USB Clock UDPCK • all the peripheral clocks, independently controllable • four programmable ...
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... Offers visibility of COMMRX and COMMTX signals from the ARM Processor • Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of – Chip ID is 0x271B 0940 (VERSION 0) for AT91SAM7XC256 – Chip ID is 0x271A 0740 (VERSION 0) for AT91SAM7XC128 10.7 Period Interval Timer • 20-bit programmable counter plus 12-bit interval counter 10 ...
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PIO Controllers • Two PIO Controllers, each controlling 31 I/O lines • Fully programmable through set/clear registers • Multiplexing of two peripheral functions per I/O line • For each I/O line (whether assigned to a peripheral or used as ...
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Peripherals 11.1 Peripheral Mapping Each peripheral is allocated 16 Kbytes of address space. Figure 11-1. User Peripheral Mapping 6209AS–ATARM–20-Oct-05 AT91SAM7XC256/128 Preliminary 0xF000 0000 Reserved 0xFFF9 FFFF 0xFFFA 0000 TC0, TC1, TC2 0xFFFA 3FFF 0xFFFA 4000 AES 128 0xFFFA 7FFF ...
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Peripheral Multiplexing on PIO Lines The AT91SAM7XC256/128 features two PIO controllers, PIOA and PIOB, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls 31 lines. Each line can be assigned to one of two peripheral ...
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PIO Controller A Multiplexing Table 11-1. Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 RXD0 PA1 TXD0 PA2 SCK0 PA3 RTS0 PA4 CTS0 PA5 RXD1 PA6 TXD1 PA7 SCK1 PA8 RTS1 PA9 CTS1 PA10 ...
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PIO Controller B Multiplexing Table 11-2. Multiplexing on PIO Controller B PIO Controller A I/O Line Peripheral A PB0 ETXCK/EREFCK PB1 ETXEN PB2 ETX0 PB3 ETX1 PB4 ECRS PB5 ERX0 PB6 ERX1 PB7 ERXER PB8 EMDC PB9 EMDIO PB10 ...
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Peripheral Identifiers The AT91SAM7XC256/128 embeds a wide range of peripherals. eral Identifiers of the AT91SAM7XC256/128. Unique peripheral identifiers are defined for both the Advanced Interrupt Controller and the Power Management Controller. Table 11-3. Peripheral ...
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Ethernet MAC • DMA Master on Receive and Transmit Channels • Compatible with IEEE Standard 802.3 • 10 and 100 Mbit/s operation • Full- and half-duplex operation • Statistics Counter Registers • MII/RMII interface to the physical layer • ...
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One, two or three bytes for slave address • Sequential read/write operations 11.9 USART • Programmable Baud Rate Generator • 9-bit full-duplex synchronous or asynchronous serial communications – stop bits in Asynchronous Mode ...
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Delay timing – Pulse Width Modulation – Up/down capabilities • Each channel is user-configurable and contains: – Three external clock inputs • Five internal clock inputs, as defined in Table 11-4. TC Clock input TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 ...
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CAN Controller • Fully compliant with CAN 2.0A and 2.0B • Bit rates up to 1Mbit/s • Eight object oriented mailboxes each with the following properties: – CAN Specification 2.0 Part A or 2.0 Part B Programmable for each ...
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Cycles Encryption/Decryption Processing Time for DES • 50-clock Cycles Encryption/Decryption Processing Time for TDES • Support the Four Standard Modes of Operation specified in the FIPS Publication 81, DES • Modes of Operation: – Electronic Codebook (ECB) – ...
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... Table 12-1. Ordering Information Ordering Code AT91SAM7XC256-AU AT91SAM7XC128-AU 13. Export Regulations Statement These commodities, technology or software will be exported from France and the applicable Export Administration Regulations will apply. French, United States and other relevant laws, reg- ulations and requirements regarding the export of products may restrict sale, export and re- export of these products ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...