AT91SAM7SE256 ATMEL [ATMEL Corporation], AT91SAM7SE256 Datasheet - Page 19

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AT91SAM7SE256

Manufacturer Part Number
AT91SAM7SE256
Description
Product Description
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet

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7.6
7.7
6222ES–ATARM–15-Dec-09
SDRAM Controller
Error Corrected Code Controller
• Multiple device adaptability
• Multiple Wait State Management
• Numerous configurations supported
• Programming facilities
• Energy-saving capabilities
• Error detection
• SDRAM Power-up Initialization by software
• Latency is set to two clocks (CAS Latency of 1, 3 Not Supported)
• Auto Precharge Command not used
• Mobile SDRAM supported (except for low-power extended mode and deep power-down
• Tracking the accesses to a NAND Flash device by triggering on the corresponding chip select
• Single bit error correction and 2-bit Random detection.
• Automatic Hamming Code Calculation while writing
• Automatic Hamming Code Calculation while reading
mode)
– Compliant with LCD Module
– Compliant with PSRAM in synchronous operations
– Programmable Setup Time Read/Write
– Programmable Hold Time Read/Write
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with two or four Internal Banks
– SDRAM with 16- or 32-bit Data Path
– Word, half-word, byte access
– Automatic page break when Memory Boundary has been reached
– Multibank Ping-pong Access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
– Self-refresh, and Low-power Modes supported
– Refresh Error Interrupt
– ECC value available in a register
– Error Report, including error flag, correctable error flag and word address being
– Supports 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-byte
AT91SAM7SE512/256/32 Preliminary Summary
detected erroneous
pages
19

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