ATMEGA325-16AJ ATMEL [ATMEL Corporation], ATMEGA325-16AJ Datasheet - Page 208

• Manufacturer Part Number: ATMEGA325-16AJ
• Description: 8-bit Microcontroller with In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

The ADC Data Register –
ADCL and ADCH
ADLAR = 0
ADLAR = 1
ADC Control and Status
Register B – ADCSRB
208
ATmega325/3250/645/6450
When an ADC conversion is complete, the result is found in these two registers. When
ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently,
if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to
read ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is
read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared
(default), the result is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in “ADC Conversion
Result” on page 203.
• Bit 7 – Res: Reserved Bit
This bit is reserved for future use. To ensure compatibility with future devices, this bit
must be written to zero when ADCSRB is written.
• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will
trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no
effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag.
Note that switching from a trigger source that is cleared to a trigger source that is set,
will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will
start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trig-
ger event, even if the ADC Interrupt Flag is set
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
ADC7
ADC9
ADC1
15
15
R
R
R
R
–
7
0
0
7
0
0
R
7
–
0
ADC6
ADC8
ADC0
ACME
R/W
14
14
R
R
R
R
–
6
0
0
6
0
0
6
0
ADC5
ADC7
13
13
R
R
R
R
–
5
0
0
–
5
0
0
R
5
–
0
ADC4
ADC6
12
12
R
R
R
R
–
4
0
0
–
4
0
0
R
4
–
0
.
ADC3
ADC5
11
11
–
3
R
R
0
0
–
3
R
R
0
0
R
3
–
0
ADTS2
ADC2
ADC4
R/W
10
10
R
R
R
R
–
2
0
0
–
2
0
0
2
0
ADTS1
ADC9
ADC1
ADC3
R/W
9
1
R
R
0
0
9
–
1
R
R
0
0
1
0
ADTS0
ADC8
ADC0
ADC2
R/W
R
R
R
R
8
0
0
0
8
–
0
0
0
0
0
2570A–AVR–09/04
ADCSRB
ADCH
ADCH
ADCL
ADCL