T89C51CC02_0305 ATMEL [ATMEL Corporation], T89C51CC02_0305 Datasheet
T89C51CC02_0305
Related parts for T89C51CC02_0305
T89C51CC02_0305 Summary of contents
Page 1
Features • 80C51 Core Architecture • 256 Bytes of On-chip RAM • 256 Bytes of On-chip XRAM • 16K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Erase/Write Cycle: 100K • 2K Bytes of On-chip ...
Page 2
Description Block Diagram XTAL1 XTAL2 CPU T89C51CC02 2 TM Part of the CANary family of 8-bit microcontrollers dedicated to CAN network applica- tions, the T89C51CC02 is a low-pin count 8-bit Flash microcontroller Mode a maximum external clock rate ...
Page 3
Pin Configurations P4.0/TxDC P3.3/INT1 4126D–CAN–05/03 VAREF 28 1 P1.0/AN0/T2 VAGND 2 27 P1.1/AN1/T2EX 26 P1.2/AN2/ECI VAVCC 3 25 P1.3/AN3/CEX0 P4.1/RxDC 4 P1.4/AN4/CEX1 P4.0/TxDC 24 5 P1.5/AN5 23 P2.1 6 P1.6/AN6 22 7 P3.7 SO28 P1.7/AN7 8 21 P3.6 P2.0 P3.5/T1 ...
Page 4
T89C51CC02 4 24 P4.0/TxDC P3.7 3 P3.6 QFP- P3.5/ P3.4/ P3.3/INT1 8 P1.3/AN3/CEX0 P1.4/AN4/CEX1 P1.5/AN5 P1.6/AN6 P1.7/AN7 P2.0 NC RESET 4126D–CAN–05/03 ...
Page 5
Pin Description Pin Name Type Description VSS GND Circuit ground VCC Supply Voltage VAREF Reference Voltage for ADC VAVCC Supply Voltage for ADC VAGND Reference Ground for ADC P1.0:7 I/O Port 8-bit bi-directional I/O port with internal ...
Page 6
Pin Name Type Description P3.0:7 I/O Port 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs ...
Page 7
I/O Configurations Port Structure 4126D–CAN–05/03 Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A CPU ’write to latch’ signal initiates transfer of internal bus data into the type-D latch. A CPU ...
Page 8
Read-Modify-Write Instructions Quasi Bi-directional Port Operation T89C51CC02 8 Some instructions read the latch data rather than the pin data. The latch based instruc- tions read the data, modify the data and then rewrite the latch. These are called ’Read- Modify-Write’ ...
Page 9
This is traditional CMOS switch convention. Current strengths are 1/10 that of pFET #3. Note: During Reset, pFET#1 is not avtivated. During Reset, only the weak pFET#3 pull up the pin. Figure 2. Internal ...
Page 10
SFR Mapping Table 2. C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word SP 81h Stack Pointer Data Pointer Low byte DPL 82h LSB of DPTR Data Pointer High byte DPH ...
Page 11
Table 4. Timers SFRs (Continued) Mnemonic Add Name Timer/Counter 2 T2CON C8h control Timer/Counter 2 T2MOD C9h Mode Timer/Counter 2 RCAP2H CBh Reload/Capture High byte Timer/Counter 2 RCAP2L CAh Reload/Capture Low byte WatchDog Timer WDTRST A6h Reset WatchDog Timer WDTPRG ...
Page 12
Table 6. PCA SFRs (Continued) Mnemonic Add Name PCA Compare CCAP0L EAh Capture Module 0 L CCAP1L EBh PCA Compare Capture Module 1 L Table 7. Interrupt SFRs Mnemonic Add Name Interrupt Enable IEN0 A8h Control 0 Interrupt Enable IEN1 ...
Page 13
Table 9. CAN SFRs (Continued) Mnemonic Add Name CAN Enable CANEN CFh Channel byte CAN General CANGIE C1h Interrupt Enable CAN Interrupt CANIE C3h Enable Channel byte CAN Status Interrupt CANSIT BBh Channel byte CANTCON A1h CAN Timer Control CANTIMH ...
Page 14
Table 9. CAN SFRs (Continued) Mnemonic Add Name CAN Identifier Mask byte 2(PartA) CANIDM2 C5h CAN Identifier Mask byte 2(PartB) CAN Identifier Mask byte 3(PartA) CANIDM3 C6h CAN Identifier Mask byte 3(PartB) CAN Identifier Mask byte 4(PartA) CANIDM4 C7h CAN ...
Page 15
Table 11. SFR Mapping (1) 0/8 1/9 IPL1 CH F8h xxxx x000 0000 0000 B F0h 0000 0000 IEN1 CL E8h xxxx x000 0000 0000 ACC E0h 0000 0000 CCON CMOD D8h 0000 0000 0xxx x000 PSW FCON D0h 0000 ...
Page 16
Clock Description T89C51CC02 16 The T89C51CC02 core needs only 6 clock periods per machine cycle. This feature, called “X2”, provides the following advantages: • Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. • Saves power ...
Page 17
Figure 3. Clock CPU Generation Diagram Hardware Byte XTAL1 XTAL2 PD PCON.1 ÷ 2 ÷ CKCON.0 CANX2 CKCON.7 CKCON.6 4126D–CAN–05/03 X2B PCON.0 On RESET IDL X2 CKCON.0 ÷ ÷ 2 ÷ ...
Page 18
Figure 4. Mode Switching Waveforms XTAL1 XTAL2 X2 bit CPU clock STD Mode Note order to prevent any incorrect operation while operating in the X2 Mode, users must be aware that all peripherals using the clock frequency as ...
Page 19
Register 4126D–CAN–05/03 Table 12. CKCON Register CKCON (S:8Fh) Clock Control Register CANX2 WDX2 PCAX2 Bit Bit Number Mnemonic Description (1) CAN Clock 7 CANX2 Clear to select 6 clock periods per peripheral clock cycle. Set to select ...
Page 20
Power Management Reset Pin At Power-up (cold reset) T89C51CC02 20 Two power reduction modes are implemented in the T89C51CC02: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction ...
Page 21
During a Normal Operation (Warm Reset) Watchdog Reset 4126D–CAN–05/03 Table 14. Minimum Reset Capacitor for a 15k Pull-down Resistor oscrst/vddrst 1ms 5ms 2.7µF 20ms 10µF Note: These values assume VDD starts from 0v to the nominal value. If the time ...
Page 22
Reset Recommendation to Prevent Flash Corruption Idle Mode Entering Idle Mode Exiting Idle Mode Power-down Mode Entering Power-down Mode T89C51CC02 22 When a Flash program memory is embedded on-chip strongly recommended to use an external reset chip (brown ...
Page 23
Exiting Power-down Mode Figure 8. Power-down Exit Waveform Using INT1:0# INT1:0# OSC Active phase 4126D–CAN–05/03 V Note: If was reduced during the Power-down mode, do not exit Power-down mode until restored to the normal operating level. DD ...
Page 24
Registers T89C51CC02 24 Table 15. PCON Register PCON (S:87h) Power Control Register SMOD1 SMOD0 - Bit Bit Number Mnemonic Description Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode 1, 2 ...
Page 25
Data Memory Internal Space Lower 128 Bytes RAM 4126D–CAN–05/03 The T89C51CC02 provides data memory access in two different spaces: The internal space mapped in three separate segments: • The lower 128 Bytes RAM segment. • The upper 128 Bytes RAM ...
Page 26
Upper 128 Bytes RAM Expanded RAM T89C51CC02 26 Figure 10. Lower 128 Bytes Internal RAM Organization 30h 20h 18h 10h 08h 00h The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect addressing mode. ...
Page 27
Dual Data Pointer Description Application 4126D–CAN–05/03 The T89C51CC02 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR0 and DPTR1 are Seen by the CPU as ...
Page 28
Registers T89C51CC02 28 Table 17. PSW Register PSW (S:D0h) Program Status Word Register Bit Bit Number Mnemonic Description Carry Flag 7 CY Carry out from bit 1 of ALU operands. Auxiliary Carry Flag 6 ...
Page 29
Table 18. AUXR1 Register AUXR1 (S:A2h) Auxiliary Control Register ENBOOT Bit Bit Number Mnemonic Description Reserved The value read from these bits is indeterminate. Do not set these bits. ...
Page 30
EEPROM Data Memory Write Data in the Column Latches Programming Read Data T89C51CC02 30 The 2K bytes on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/XRAM memory space and is selected by setting control bits ...
Page 31
Examples 4126D–CAN–05/03 ;*F************************************************************************* ;* NAME: api_rd_eeprom_byte ;* DPTR contain address to read. ;* Acc contain the reading value ;* NOTE: before execute this function, be sure the EEPROM is not BUSY ;*************************************************************************** api_rd_eeprom_byte: ; Save and clear EA MOV EECON, ...
Page 32
Registers T89C51CC02 32 Table 19. EECON Register EECON (S:0D2h) EEPROM Control Register EEPL3 EEPL2 EEPL1 Bit Bit Number Mnemonic Description Programming Launch Command bits EEPL3-0 Write 5Xh followed by AXh to EEPL to launch ...
Page 33
Program/Code Memory Flash Memory Architecture Figure 13. Flash Memory Architecture Hardware Security (1 byte) Extra Row (128 Bytes) Column Latches (128 Bytes) 4126D–CAN–05/03 The T89C51CC02 implement 16K Bytes of on-chip program/code memory. The Flash memory increases EPROM and ROM functionality ...
Page 34
FM0 Memory Architecture User Space Extra Row (XRow) Hardware Security Byte Column Latches Cross Flash Memory Access Description T89C51CC02 34 The Flash memory is made blocks (See Figure 13): 1. The memory array (user space) 16K Bytes ...
Page 35
Overview of FM0 Operations Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column Launching Programming 4126D–CAN–05/03 The CPU interfaces the Flash memory through the FCON register and AUXR1 register. ...
Page 36
Status of the Flash Memory Selecting FM1 Loading the Column Latches T89C51CC02 36 The bit FBUSY in FCON register is used to indicate the status of programming. FBUSY is set when programming is in progress. The bit ENBOOT in AUXR1 ...
Page 37
Programming the Flash Spaces User Extra Row 4126D–CAN–05/03 Figure 14. Column Latches Loading Procedure Note: 1. The last page address used when loading the column latch is the one used to select the page programming address. The following procedure is ...
Page 38
Hardware Security Byte T89C51CC02 38 Figure 15. Flash and Extra row Programming Procedure The following procedure is used to program the Hardware and is summarized in Figure 16: • Set FPS and map Hardware byte (FCON = 0x0C) • Save ...
Page 39
Reading the Flash Spaces User Extra Row Hardware Security Byte 4126D–CAN–05/03 Figure 16. Hardware Programming Procedure Flash Spaces Programming Save & Disable FCON = 0Ch Data Load DPTR = 00h ACC = Data Exec: MOVX @DPTR, ...
Page 40
Flash Protection from Parallel Programming Preventing Flash Corruption T89C51CC02 40 Figure 17. Reading Procedure Note for the Hardware Security Byte. The three lock bits in Hardware Security Byte (See ’In-System Programming’ section) are programmed according to Table ...
Page 41
Registers 4126D–CAN–05/03 Table 24. FCON Register FCON Register FCON (S:D1h) Flash Control Register FPL3 FPL2 FPL1 Bit Bit Number Mnemonic Description Programming Launch Command bits FPL3:0 Write 5Xh followed by AXh to launch the ...
Page 42
In-System Programming (ISP) Flash Programming and Erasure T89C51CC02 42 With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash technology the T89C51CC02 allows the system engineer the development of applica- tions with a very high ...
Page 43
Boot Process Software Boot Process Example Figure 19. Hardware Boot Process Algorithm ENBOOT = 0000h Application in FM0 Application- Programming-Interface 4126D–CAN–05/03 Many algorithms can be used for the software boot process. Below are descriptions of the different ...
Page 44
XROW Bytes Hardware Conditions T89C51CC02 44 The EXTRA ROW (XROW) includes 128 bytes. Some of these bytes are used for spe- cific purpose in conjonction with the bootloader. Table 25. XROW Mapping Description Copy of the Manufacturer Code Copy of ...
Page 45
Hardware Security Byte 4126D–CAN–05/03 Table 26. Hardware Security byte X2B BLJB - Bit Bit Number Mnemonic Description X2 bit 7 X2B Set this bit to start in standard mode Clear this bit to start in X2 Mode. ...
Page 46
Serial I/O Port Figure 20. Serial I/O Port Block Diagram TXD RXD Framing Error Detection T89C51CC02 46 The T89C51CC02 I/O serial port is compatible with the I/O serial port in the 80C52. It provides both synchronous and asynchronous communication modes. ...
Page 47
Automatic Address Recognition Given Address 4126D–CAN–05/03 Figure 22. UART Timing in Mode 1 RXD D0 D1 Start bit RI SMOD0 = x FE SMOD0 = 1 Figure 23. UART Timing in Modes 2 and 3 RXD D0 D1 Start bit ...
Page 48
Broadcast Address T89C51CC02 48 Here is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0010b SADEN1111 1101b Given1111 00X1b The ...
Page 49
Registers 4126D–CAN–05/03 Table 27. SCON Register SCON (S:98h) Serial Control Register FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Description Framing Error bit (SMOD0 = Clear to reset the error state, not cleared by a ...
Page 50
T89C51CC02 50 Table 28. SADEN Register SADEN (S:B9h) Slave Address Mask Register Bit Bit Number Mnemonic Description Mask Data for Slave Individual Address Reset Value = 0000 0000b Not bit addressable Table 29. SADDR ...
Page 51
Table 31. PCON Register PCON (S:87h) Power Control Register SMOD1 SMOD0 - Bit Bit Number Mnemonic Description Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode ...
Page 52
Timers/Counters Timer/Counter Operations Timer 0 T89C51CC02 52 The T89C51CC02 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an ...
Page 53
Mode 0 (13-bit Timer) Figure 24. Timer/Counter x ( Mode 0 See section “Clock” FTx ÷ 6 CLOCK Tx C/Tx# TMOD Reg INTx# GATEx TMOD Reg Mode 1 (16-bit Timer) Figure 25. Timer/Counter x (x= 0 ...
Page 54
Figure 26. Timer/Counter x ( Mode 2 See section “Clock” FTx ÷ 6 CLOCK Tx C/Tx# TMOD Reg INTx# GATEx TMOD Reg Mode 3 (Two 8-bit Timers) Figure 27. Timer/Counter 0 in Mode 3: Two 8-bit ...
Page 55
Mode 0 (13-bit Timer) Mode 1 (16-bit Timer) Mode 2 (8-bit Timer with Auto- Reload) Mode 3 (Halt) Interrupt 4126D–CAN–05/03 • For normal Timer operation (GATE1= 0), setting TR1 allows TL1 to be incremented by the selected input. Setting GATE1 ...
Page 56
Registers T89C51CC02 56 Table 32. TCON Register TCON (S:88h) Timer/Counter Control Register TF1 TR1 TF0 Bit Bit Number Mnemonic Description Timer 1 Overflow Flag 7 TF1 Cleared by hardware when processor vectors to interrupt routine. Set by ...
Page 57
Table 33. TMOD Register TMOD (S:89h) Timer/Counter Mode Control Register GATE1 C/T1# M11 Bit Bit Number Mnemonic Description Timer 1 Gating Control bit 7 GATE1 Clear to enable Timer 1 whenever TR1 bit is set. Set ...
Page 58
T89C51CC02 58 Table 35. TL0 Register TL0 (S:8Ah) Timer 0 Low Byte Register Bit Bit Number Mnemonic Description 7:0 Low Byte of Timer 0 Reset Value = 0000 0000b Table 36. TH1 Register TH1 (S:8Dh) Timer 1 ...
Page 59
Timer 2 Auto-Reload Mode Figure 29. Auto-Reload Mode Up/Down Counter See section “Clock” FT2 CLOCK T2 4126D–CAN–05/03 The T89C51CC02 Timer 2 is compatible with Timer 2 in the 80C52 16-bit timer/counter: the count is maintained by two ...
Page 60
Programmable Clock- Output T89C51CC02 60 In clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock genera- tor (Figure 30). The input clock increments TL2 at frequency f repeatedly counts to overflow from a loaded value. At overflow, the contents ...
Page 61
Registers 4126D–CAN–05/03 Table 38. T2CON Register T2CON (S:C8h) Timer 2 Control Register TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 Overflow Flag TF2 is not set if RCLK=1 or TCLK = 1. 7 TF2 Must ...
Page 62
T89C51CC02 62 Table 39. T2MOD Register T2MOD (S:C9h) Timer 2 Mode Control Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. ...
Page 63
Table 41. TL2 Register TL2 (S:CCh) Timer 2 Low Byte Register Bit Bit Number Mnemonic Description Low Byte of Timer 2 Reset Value = 0000 0000b Not bit addressable Table ...
Page 64
Watchdog Timer Figure 31. Watchdog Timer RESET Fwd Clock WDTPRG - T89C51CC02 64 T89C51CC02 contains a powerful programmable hardware Watchdog Timer (WDT) that automatically resets the chip if it software fails to reset the WDT before the selected time interval ...
Page 65
Watchdog Programming 4126D–CAN–05/03 The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the WDT duration. Table 44. Machine Cycle Count ...
Page 66
Watchdog Timer During Power-down Mode and Idle Register T89C51CC02 66 In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are 2 methods of ...
Page 67
Table 47. WDTRST Register WDTRST (S:A6h Write Only) – Watchdog Timer Enable register Bit Bit Number Mnemonic Description 7 - Watchdog Control Value Reset Value = 1111 1111b Note: The WDRST register is ...
Page 68
CAN Controller CAN Controller Description Figure 32. CAN Controller Block Diagram TxDC RxDC T89C51CC02 68 The CAN Controller provides all the features required to implement the serial communi- cation protocol CAN as defined by BOSCH GmbH. The CAN specification as ...
Page 69
CAN Controller Mailbox and Registers Organization Figure 33. CAN Controller Memory Organization SFRs General Control General Status General Interrupt bit Timing - 1 bit Timing - 2 bit Timing - 3 Enable message object Enable Interrupt Enable Interrupt message object ...
Page 70
Working on Message Objects CAN Controller Management T89C51CC02 70 The Page message object register (CANPAGE) is used to select one of the 4 message objects. Then, message object Control (CANCONCH) and message object Status (CANSTCH) are available for this selected ...
Page 71
Buffer Mode IT CAN Management 4126D–CAN–05/03 Any message object can be used to define one buffer, including non-consecutive mes- sage objects, and with no limitation in number of message objects used Each message object of the buffer ...
Page 72
Figure 35. CAN Controller Interrupt Structure CANGIE.5 ENRX RXOK i CANSTCH.5 TXOK i CANSTCH.6 BERR i CANSTCH.4 SERR i CANSTCH.3 CERR i CANSTCH.2 FERR i CANSTCH.1 AERR i CANSTCH.0 OVRBUF CANGIT.4 SERG CANGIT.3 CERG CANGIT.2 FERG CANGIT.1 AERG CANGIT.0 OVRTIM ...
Page 73
Timing and Baud Rate Figure 36. Sample and Transmission Point FCAN Prescaler BRP CLOCK 4126D–CAN–05/03 To enable an interrupt on Buffer-full condition: • Enable General CAN IT in the interrupt system register • Enable interrupt on Buffer full, ENBUF ...
Page 74
Figure 37. General Structure of a bit Period Oscillator System Clock Data (1) Phase error ≤ 0 (2) Phase error ≥ 0 (3) Phase error > 0 (4) Phase error < 0 T89C51CC02 74 1/ Fcan bit Rate Prescaler Tscl ...
Page 75
Fault Confinement 4126D–CAN–05/03 With respect to fault confinement, a unit may be in one of the three following status: • Error active • Error passive • Bus off An error active unit takes part in bus communication and can send ...
Page 76
Acceptance Filter T89C51CC02 76 Upon a reception hit (i.e., a good comparison between the ID+RTR+RB+IDE received and an ID+RTR+RB+IDE specified while taking the comparison mask into account) the ID+RTR+RB+IDE received are written over the ID TAG Registers. ID => IDT0-29 ...
Page 77
Data and Remote Frame message object in transmission message object stay in transmission message object in transmission message object in reception by CAN controller message object stay in reception message object in transmission message object in reception by CAN controller ...
Page 78
Time Trigger Communication (TTC) and Message Stamping Figure 40. Block Diagram of CAN Timer Fcan ÷ 6 CLOCK TXOK i CANSTCH.4 RXOK i CANSTCH.5 CANSTMPH & CANSTMPL T89C51CC02 78 The T89C51CC02 has a programmable 16-bit Timer (CANTIMH&CANTIML) for mes- sage ...
Page 79
CAN Autobaud and Listening Mode Routine Examples 4126D–CAN–05/03 To activate the Autobaud feature, the AUTOBAUD bit in the CANGCON register must be set. In this mode, the CAN controller is only listening to the line without acknowledg- ing the received ...
Page 80
T89C51CC02 80 // Enable the CAN macro CANGCON = 02h 2. Configure message object 3 in reception to receive only standard (11bit identifier) message 100h // Select the message object 3 CANPAGE = 30h // Enable the interrupt on this ...
Page 81
Find the first message object which generate an interrupt in CANSIT // Select the corresponding message object // Analyse the CANSTCH register to identify which kind of interrupt is generated // Manage the interrupt // Clear the status ...
Page 82
CAN SFRs Table 49. SFR Mapping (1) 0/8 1/9 IPL1 CH F8h xxxx x000 0000 0000 B F0h 0000 0000 IEN1 CL E8h xxxx x000 0000 0000 ACC E0h 0000 0000 CCON CMOD D8h 0000 0000 0xxx x000 PSW FCON ...
Page 83
Registers 4126D–CAN–05/03 Table 50. CANGCON Register CANGCON (S:ABh) CAN General Control Register ABRQ OVRQ TTC Bit Number Bit Mnemonic Description Abort Request Not an auto-resetable bit. A reset of the ENCH bit (message object control & DLC ...
Page 84
T89C51CC02 84 Table 51. CANGSTA Register CANGSTA (S:AAh) CAN General Status Register OVFG - Bit Number Bit Mnemonic Description Reserved 7 - The values read from this bit is indeterminate. Do not set this bit. Overload ...
Page 85
Table 52. CANGIT Register CANGIT (S:9Bh) CAN General Interrupt CANIT - OVRTIM Bit Number Bit Mnemonic Description General interrupt flag This status bit is the image of all the CAN controller interrupts sent 7 CANIT to ...
Page 86
T89C51CC02 86 Table 53. CANTEC Register CANTEC (S:9Ch Read Only) – CAN Transmit Error Counter TEC7 TEC6 TEC5 Bit Number Bit Mnemonic Description Transmit Error Counter TEC7:0 See Figure 38 Reset Value = 00h ...
Page 87
Table 55. CANGIE Register CANGIE (S:C1h) – CAN ENRX Bit Number Bit Mnemonic Description Reserved The values read from these bits are indeterminate. Do not set these bits. Enable Receive ...
Page 88
T89C51CC02 88 Table 56. CANEN Register CANEN (S:CFh Read Only) CAN Enable Message Object Registers Bit Number Bit Mnemonic Description Reserved The values read from these bits are indeterminate. ...
Page 89
Table 58. CANIE Register CANIE (S:C3h) – CAN Enable Interrupt message object Registers Bit Number Bit Mnemonic Description Reserved The values read from these bits are indeterminate. Do ...
Page 90
T89C51CC02 90 Table 60. CANBT2 Register CANBT2 (S:B5h) – CAN bit Timing Registers SJW 1 SJW 0 Bit Number Bit Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not ...
Page 91
Table 61. CANBT3 Register CANBT3 (S:B6h) CAN bit Timing Registers PHS2 2 PHS2 1 Bit Number Bit Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this ...
Page 92
T89C51CC02 92 Table 62. CANPAGE Register CANPAGE (S:B1h) – CAN Message Object Page Register CHNB 1 Bit Number Bit Mnemonic Description Reserved The values read from these bits are indeterminate. Do ...
Page 93
Table 64. CANSTCH Register CANSTCH (S:B2h) – CAN Message Object Status Register DLCW TXOK RXOK Bit Number Bit Mnemonic Description Data Length Code Warning The incoming message does not have the DLC expected. 7 DLCW Whatever ...
Page 94
T89C51CC02 94 Table 65. CANIDT1 Register for V2.0 part A CANIDT1 for V2.0 part A (S:BCh) – CAN Identifier Tag Registers IDT 10 IDT 9 IDT 8 Bit Number Bit Mnemonic Description IDentifier Tag Value 7 ...
Page 95
Table 68. CANIDT1 for V2.0 part A CANIDT4 for V2.0 part A (S:BFh) CAN Identifier Tag Registers Bit Number Bit Mnemonic Description Reserved The values read from these ...
Page 96
T89C51CC02 96 Table 71. CANIDT3 Register for V2.0 Part B CANIDT3 for V2.0 Part B (S:BEh) CAN Identifier Tag Registers IDT 12 IDT 11 IDT 10 Bit Number Bit Mnemonic Description IDentifier Tag Value 7 - ...
Page 97
Table 73. CANIDM1 Register for V2.0 part A CANIDM1 for V2.0 part A (S:C4h) CAN Identifier Mask Registers IDMSK 10 IDMSK 9 IDMSK 8 Bit Number Bit Mnemonic Description IDentifier Mask Value 0 - comparison ...
Page 98
T89C51CC02 98 Table 76. CANIDM4 Register for V2.0 part A CANIDM4 for V2.0 part A (S:C7h) CAN Identifier Mask Registers Bit Number Bit Mnemonic Description Reserved The values read ...
Page 99
Table 78. CANIDM2 Register for V2.0 Part B CANIDM2 for V2.0 Part B (S:C5h) CAN Identifier Mask Registers IDMSK 20 IDMSK 19 IDMSK 18 Bit Number Bit Mnemonic Description IDentifier Mask Value 0 - comparison ...
Page 100
T89C51CC02 100 Table 80. CANIDM4 Register for V2.0 Part B CANIDM4 for V2.0 Part B (S:C7h) CAN Identifier Mask Registers IDMSK 4 IDMSK 3 IDMSK 2 Bit Number Bit Mnemonic Description IDentifier Mask Value 0 - ...
Page 101
Table 82. CANTCON Register CANTCON (S:A1h) CAN Timer ClockControl TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 Bit Number Bit Mnemonic Description Timer Prescaler of CAN Timer This register is a prescaler for the main timer ...
Page 102
T89C51CC02 102 Table 85. CANSTMPH Register CANSTMPH (S:AFh Read Only) CAN Stamp Timer High TIMSTMP TIMSTMP TIMSTMP Bit Number Bit Mnemonic Description High byte of Time Stamp TIMSTMP15:8 See Figure 40. ...
Page 103
Programmable Counter Array (PCA) PCA Timer 4126D–CAN–05/03 The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves ...
Page 104
Figure 42. PCA Timer/Counter FPca/6 FPca/2 T0 OVF P1.2 Idle T89C51CC02 104 CIDL CPS1 CPS0 CF CR The CMOD register includes three additional bits associated with the PCA. • The CIDL bit which allows the PCA to stop during idle ...
Page 105
PCA Modules 4126D–CAN–05/03 Each one of the two compare/capture modules has six possible functions. It can perform: • 16-bit Capture, positive-edge triggered • 16-bit Capture, negative-edge triggered • 16-bit Capture, both positive and negative-edge triggered • 16-bit Software Timer • ...
Page 106
PCA Interrupt Figure 43. PCA Interrupt System PCA Timer/Counter Module 0 Module 1 ECF CMOD.0 PCA Capture Mode Figure 44. PCA Capture Mode CEXn T89C51CC02 106 CF CR ECCFn CCAPMn.0 To use one of the PCA ...
Page 107
Software Timer Mode Figure 45. PCA 16-bit Software Timer and High Speed Output Mode PCA Counter CH (8 bits) (8 bits) “0” Reset Write to “1” CCAPnL Write to CCAPnH 4126D–CAN–05/03 The PCA modules can be used as software ...
Page 108
High Speed Output Mode Figure 46. PCA High Speed Output Mode Write to CCAPnH Reset Write to CCAPnL “0” “1” Enable Pulse Width Modulator Mode T89C51CC02 108 In this mode the CEX output (on port 1) associated with the PCA ...
Page 109
Figure 47. PCA PWM Mode CL rolls over from FFh TO 00h loads CCAPnH contents into CCAPnL CL (8 bits) 4126D–CAN–05/03 CCAPnH CCAPnL “0” CL < CCAPnL 8-bit Comparator CL >= CCAPnL “1” ECOMn PWMn CCAPMn.6 CCAPMn.1 T89C51CC02 CEX 109 ...
Page 110
PCA Registers T89C51CC02 110 Table 89. CMOD Register CMOD (S:D9h) PCA Counter Mode Register CIDL - - Bit Bit Number Mnemonic Description PCA Counter Idle Control bit 7 CIDL Clear to let the PCA run during Idle ...
Page 111
Table 90. CCON Register CCON (S:D8h) PCA Counter Control Register Bit Number Bit Mnemonic Description PCA Timer/Counter Overflow flag Set by hardware when the PCA Timer/Counter rolls over. This 7 CF generates a ...
Page 112
T89C51CC02 112 Table 91. CCAPnH Registers CCAP0H (S:FAh) CCAP1H (S:FBh) PCA High Byte Compare/Capture Module n Register (n=0.. CCAPnH 7 CCAPnH 6 CCAPnH 5 CCAPnH 4 Bit Number Bit Mnemonic Description 7:0 CCAPnH 7:0 High byte of ...
Page 113
Table 93. CCAPMn Registers CCAPM0 (S:DAh) CCAPM1 (S:DBh) PCA Compare/Capture Module n Mode registers (n=0.. ECOMn CAPPn Bit Number Bit Mnemonic Description Reserved 7 - The Value read from this bit is indeterminate. Do not ...
Page 114
T89C51CC02 114 Table 94. CH Register CH (S:F9h) PCA Counter Register High value Bit Number Bit Mnemonic Description 7:0 CH 7:0 High byte of Timer/Counter Reset Value = 0000 00000b Table ...
Page 115
Analog-to-Digital Converter (ADC) Features ADC Port1 I/O Functions 4126D–CAN–05/03 This section describes the on-chip 10-bit analog-to-digital converter of the T89C51CC02. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ...
Page 116
Figure 48. ADC Description ADC CLOCK AN0/P1.0 000 AN1/P1.1 001 AN2/P1.2 010 AN3/P1.3 011 AN4/P1.4 100 AN5/P1.5 101 AN6/P1.6 110 AN7/P1.7 111 SCH2 SCH1 ADCON.2 ADCON.1 Figure 49. Timing Diagram CLK ADEN T SETUP ADSST ADEOC Note: Tsetup min = ...
Page 117
Voltage Conversion Clock Selection Figure 50. A/D Converter Clock CPU CLOCK CPU Core Clock Symbol ADC Standby Mode IT ADC management 4126D–CAN–05/03 The bits SCH0 to SCH2 in ADCON register are used for the analog input channel selection. Table 96. ...
Page 118
Routine Examples T89C51CC02 118 Figure 51. ADC interrupt structure ADEOC ADCON.2 1. Configure P1.2 and P1.3 in ADC channels // configure channel P1.2 and P1.3 for ADC ADCF = 0Ch // Enable the ADC ADCON = 20h 2. Start a ...
Page 119
Registers 4126D–CAN–05/03 Table 97. ADCF Register ADCF (S:F6h) ADC Configuration Bit Bit Number Mnemonic Description Channel Configuration 0:7 Set to use P1.x as ADC input. Clear to ...
Page 120
T89C51CC02 120 Table 99. ADCLK Register ADCLK (S:F2h) ADC Clock Prescaler Bit Bit Number Mnemonic Description Reserved The value read from these bits are indeterminate. Do not set these bits. ...
Page 121
Interrupt System Introduction Figure 52. Interrupt Control System External INT0# Interrupt 0 Timer 0 External INT1# Interrupt 1 Timer 1 CEX0:1 PCA TxD UART RxD Timer 2 TxDC CAN Controller RxDC AIN1:0 Converter CAN Timer 4126D–CAN–05/03 The ...
Page 122
T89C51CC02 122 Each of the interrupt sources can be individually enabled or disabled by setting or clear- ing a bit in the Interrupt Enable register. This register also contains a global disable bit which must be cleared to disable all ...
Page 123
Registers 4126D–CAN–05/03 Figure 53. IEN0 Register IEN0 (S:A8h) Interrupt Enable Register ET2 Bit Bit Number Mnemonic Description Enable All Interrupt bit Clear to disable all interrupts Set to enable all interrupts. If EA=1, ...
Page 124
T89C51CC02 124 Figure 54. IEN1 Register IEN1 (S:E8h) Interrupt Enable Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 ...
Page 125
Table 104. IPL0 Register IPL0 (S:B8h) Interrupt Enable Register PPC PT2 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt Priority ...
Page 126
T89C51CC02 126 Table 105. IPL1 Register IPL1 (S:F8h) Interrupt Priority Low Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. ...
Page 127
Table 106. IPH0 Register IPH0 (B7h) Interrupt High Priority Register PPCH PT2H Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt ...
Page 128
T89C51CC02 128 Table 107. IPH1 Register IPH1 (S:F7h) Interrupt high priority Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. ...
Page 129
Electrical Characteristics Absolute Maximum Ratings I = industrial ....................................................... -40°C to 85°C Storage Temperature ................................... -65° 150°C Voltage on V from V .....................................-0. Voltage on Any Pin from V .....................-0. ...
Page 130
Power-down I is measured with all output pins disconnected; XTAL2 NC.; RST = Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature. 5. Under steady ...
Page 131
DC Parameters for A/D Converter 4126D–CAN–05/03 Figure 57. I Test Condition, Power-down Mode VaVcc RST (NC) XTAL2 XTAL1 VAGND V SS Figure 58. Clock Signal Waveform for I V -0.5V CC 0.45V T ...
Page 132
AC Parameters Serial Port Timing - Shift Register Mode T89C51CC02 132 Table 110. Symbol Description ( MHz) Symbol T XLXL T QVHX T XHQX T XHDX T XHDV Table 111. AC Parameters for a Fix Clock (F = ...
Page 133
Shift Register Timing Waveforms 0 INSTRUCTION CLOCK T QVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI External Clock Drive Characteristics (XTAL1) External Clock Drive Waveforms AC Testing Input/Output Waveforms Float Waveforms 4126D–CAN–05/ XLXL ...
Page 134
Clock Waveforms Flash Memory T89C51CC02 134 For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V ≥ ± ...
Page 135
Ordering Information T89C51CC02 134 Part Number Bootloader T89C51CC02CA-RATIM CAN T89C51CC02CA-SISIM CAN T89C51CC02CA-TDSIM CAN T89C51CC02CA-TISIM CAN T89C51CC02UA-RATIM UART T89C51CC02UA-SISIM UART T89C51CC02UA-TDSIM UART T89C51CC02UA-TISIM UART Factory default programming for T89C51CC02CA-xxxx is Bootloader CAN and HSB = BBh: • X1 mode • BLJB ...
Page 136
Package Drawings VQFP32 4126D–CAN–05/03 T89C51CC02 135 ...
Page 137
PLCC28 T89C51CC02 136 4126D–CAN–05/03 ...
Page 138
SOIC24 4126D–CAN–05/03 T89C51CC02 137 ...
Page 139
SOIC28 T89C51CC02 138 4126D–CAN–05/03 ...
Page 140
Datasheet Change Log for T89C51CC02 Changes from 4126C- 10/02 to 4126D-04/03 4126D–CAN–05/03 1. Changed the endurance of Flash to 100, 000 Write/Erase cycles. 2. Added note on Flash retention formula for V Standard Voltage", page 138. T89C51CC02 , in Section ...
Page 141
Table of Features ................................................................................................. 1 Contents Description ............................................................................................ 2 Block Diagram ....................................................................................... 2 Pin Configurations ................................................................................ 3 Pin Description...................................................................................... 5 SFR Mapping ....................................................................................... 10 Clock .................................................................................................... 16 Power Management ............................................................................ 20 Reset Pin .............................................................................................. 20 Data Memory ....................................................................................... 25 EEPROM ...
Page 142
Program/Code Memory ...................................................................... 33 In-System Programming (ISP) ........................................................... 42 Serial I/O Port ...................................................................................... 46 Timers/Counters ................................................................................. 52 Timer 2 ................................................................................................. 59 Watchdog Timer .................................................................................. 64 Watchdog Timer During Power-down Mode and Idle ...................... 66 CAN Controller .................................................................................... 68 CAN Controller ...
Page 143
CAN Controller Management ............................................................. 70 IT CAN Management.......................................................................................... 71 bit Timing and Baud Rate ................................................................................... 73 Fault Confinement .............................................................................................. 75 Acceptance Filter................................................................................................ 76 Data and Remote Frame .................................................................................... 77 Time Trigger Communication (TTC) and Message Stamping ............................ 78 CAN Autobaud ...
Page 144
Ordering Information ........................................................................ 134 Package Drawings ............................................................................ 135 Datasheet Change Log for T89C51CC01 ........................................ 139 iv VQFP32............................................................................................................ 135 PLCC28 ............................................................................................................ 136 SOIC24............................................................................................................. 137 SOIC28............................................................................................................. 138 Changes from 4126C-10/02 to 4126D-04/03 ................................................... 139 ...
Page 145
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem ...