RF6001_1 RFMD [RF Micro Devices], RF6001_1 Datasheet - Page 26

• Manufacturer Part Number: RF6001_1
• Description: FRACTIONAL-N RF SYNTHESIZER WITH MODULATOR AND DIGITAL IF FILTER
• Manufacturer: RFMD [RF Micro Devices]

RF6001
Part of the POLARIS™ TOTAL RADIO™ Solution
Slow Fine DC Adapt (SFDA)
Normally, once the FFDA timer has expired, the RF6001 fine DC correction system then holds the last value calculated until the
RX_EN transitions to low at the end of the receive burst. However, the system can be configured setting the SDI bits AD2EN
and AD2EN_2 to continue operating after the FFDA is completed in a lower bandwidth mode called the Slow Fine DC Adapt
(SFDA). In this mode, the internal adaptation update rate would normally be lowered by a factor of 48 to reduce the group delay
distortion. This SFDA rate is selected by the SDI fields ADCLK and ADCLK_2, and is adjustable from the default of 13/48MHz
up to 13MHz.
Once the fine DC adapt process is completed, the DC correction offsets internal to the RF6001 will be held until RX_EN is no
longer asserted, power is removed from the IC, or another slow adapt operation is scheduled.
Realistically, it is unlikely that the SFDA mode will be used with GSM systems. This is because the SFDA would convert a DC
error into a slowly moving AC error. Also, the GSM system will refresh the DC adapt on every frame, and thus a slow long term
correction is not necessary.
Digital Gain Control
SDI bits DAGC (3:0) can be used as a digital gain control with a range from -18dB to +60dB. This may be used to keep the
RF6001 I/Q output voltages at a constant level for those baseband IC’s that require this functionality.
Blanking
The receiver has two programmable blanking circuits. The first of these is controlled by the SDI field BLK_DLY and blanks the
output of the channel filter so that the second DC offset correction block does not see the initial transients of the receiver. This
reduces the amount of time needed to complete the second stage of the DC offset correction.
The upper line in the diagram below shows the channel filter output. The lower line shows the output of the BLK_DLY block as
input to the second DC offset correction block.
The second blanking circuit is controlled by the SDI field AGC_DLY and blanks the I and Q outputs. This avoids large startup
transients being sent to the baseband processing. The diagram below shows the action of the AGC_DLY field on the output sig-
nals.
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Rev A3 DS050929