TSI-2 AGERE [Agere Systems], TSI-2 Datasheet - Page 36

• Manufacturer Part Number: TSI-2
• Description: 2k x 2k Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

TSI-2
2k x 2k Time-Slot Interchanger
Table 6-13. CPU_Access_Error (CORWN)
Table 6-14. CPU_Access_Error_Mask (Read/Write)
36
36
Address
Address
0x00008
0x0000A
15:4 Unused.
15:4 Unused.
Bit
Bit
3
2
1
0
3
2
1
0
PLL_Lock_Error. This bit indicates if the device's master PLL is locked to the incoming CHI
reference clock (CHICLK).
0 = Locked.
1 = Not locked.
Access_Time_Out_Error.
0 = No time-out.
1 = Indicates that a time-out has occurred internal to the TFRA84J13 device on a
Invalid_Address_Error.
0 = No invalid address.
1 = Indicates that a microprocessor access to an invalid address has occurred. The address
Data_Parity_Error.
0 = No data parity error.
1 = Indicates that a microprocessor data bus parity error has occurred.
PLL_Lock_Error_Mask.
0 = The PLL_Lock_Error bit (see Table 6-13) will cause an interrupt if active.
1 = The PLL_Lock_Error bit is blocked from causing an interrupt.
Access_Time-out_Error_Mask.
0 = The Access_Time_Out_Error bit (see Table 6-13) will cause an interrupt if active.
1 = The Access_Time_Out_Error bit is blocked from causing an interrupt.
Invalid_Address_Error_Mask.
0 = The Invalid_Address_Error bit will (see Table 6-13) cause an interrupt if active.
1 = The Invalid_Address_Error bit is blocked from causing an interrupt.
Data_Parity_Error_Mask.
0 = The Data_Parity_Error bit will (see Table 6-13) cause an interrupt if active.
1 = The Data_Parity_Error bit is blocked from causing an interrupt.
microprocessor access.
causing this error can be found in the Invalid_Address_Trap register (see
page
38).
Name/Description
Name/Description
Data Sheet, Revision 3
September 21, 2005
Table 6-18 on
Agere Systems Inc.
Default
Default
—
—
—
—
—
—
1
1
1
1