A8286SETTR-TB ALLEGRO [Allegro MicroSystems], A8286SETTR-TB Datasheet - Page 11

• Manufacturer Part Number: A8286SETTR-TB
• Description: Dual LNB Supply and Control Voltage Regulator
• Manufacturer: ALLEGRO [Allegro MicroSystems]

A8286
Interrupt Request
is an open-drain, active-low output. This output may be connected
to a common IRQ line with a suitable external pull-up and can
be used with other I
from the master controller.
recognizes a fault condition, or at power-on, when the main sup-
ply, V
operating conditions. It is only reset to inactive when the I
master addresses the A8286 with the Read/Write bit set (causing a
read). Fault conditions are indicated by the TSD, VUV, and OCP
bits (when ODT is set to 1) and are latched in the Status register.
See the Status register section for full description.
bits do not cause an interrupt. All these bits are continually up-
dated, apart from the DIS bit, which changes when the LNB is
The A8286 also provides an interrupt request pin, IRQ, which
The IRQ output becomes active when either the A8286 first
The OCP (with ODT= 0), DIS, PNG, CAD and TDET status
IN
, and the internal logic supply, V
Figure 4. I
2
2
C™ Interface. Read sequences after interrupt request.
C™-compatible devices to request attention
SDA
SCL
IRQ
Fault
Event
Start
Dual LNB Supply and Control Voltage Regulator
0
1
REG
0
2
, reach the correct
0
3
Address
1
4
0
5
Read after Interrupt
A1
6
2
C™
A0
7
R
1
8
AK
9
either disabled, intentionally or due to a fault, or is enabled.
connected to the interrupt line in sequence, and then reads the
status register to determine which device is requesting attention.
The A8286 latches all conditions in the Status register until the
completion of the data read. The action at the resampling point is
further defined in the Status Register section. The bits in the Sta-
tus register are defined such that the all-zero condition indicates
that the A8286 is fully active with no fault conditions.
does not respond to any requests until the internal logic supply
V
point, the IRQ output goes active, and the VUV bit is set. After the
A8286 acknowledges the address, the IRQ flag is reset. After the
master reads the status registers, the registers are updated with the
VUV reset.
REG
D7
When the master recognizes an interrupt, it addresses all slaves
When V
has reached its operating level. Once V
D6
D5
Status Register 1
IN
D4
is initially applied, the I
D3
D2
D1
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Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com
D0
NAK
Reload
Status Register
Stop
2
C™-compatible interface
REG
has reached this
11