ICL8052A INTERSIL [Intersil Corporation], ICL8052A Datasheet
ICL8052A
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ICL8052A Summary of contents
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... TM Data Sheet 1 Precision 4 / Digit, A/D Converter 2 The ICL8052A or ICL8068A/lCL71C03 chip pairs with their multiplexed BCD output and digit drivers are ideally suited for the visual display DVM/DPM market. The outstanding digit accuracy, 200.00mV to 2.0000V full scale 2 capability, auto-zero and auto-polarity combine with true ratiometric operation, almost ideal differential linearity and time-proven dual slope conversion ...
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... Functional Block Diagram 10k 90k +15V -15V -BUF IN REF OUT 6 BUFFER INT. 3 REF 300pF + 10k ICL8052A/8068A 5 1k +BUF (TYP) REF REF CAP 1 CAP REF 7 ANALOG INPUT 10k 0 ANALOG GND 1 +5V 2 0.22 F 100k ...
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... Absolute Maximum Ratings ICL8052A, ICL8068A Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Input Voltage (8068A (8052A Input Voltage (Note Output Short Circuit Duration All Outputs (Note Indefinite ICL71C03 Power Supply Voltage (GND to V+). . . . . . . . . . . . . . . . . . . . . . 6.5V Negative Supply Voltage (GND to V -17V Analog Input Voltage (Note Digital Input Voltage (Note 4) ...
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... Negative Output Voltage Swing VOLTAGE REFERENCE Output Voltage Output Resistance Temperature Coefficient Supply Voltage (V++ -V-) Supply Current Total ICL8052A Electrical Specifications PARAMETER EACH OPERATIONAL AMPLIFIER Input Offset Voltage Input Current (Either Input) (Note 7) Common-Mode Rejection Ratio Non-Linear Component of Common-Mode Rejection Ratio (Note 8) ...
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... Equal Positive & Negative Voltage Near Full Scale) Noise (P-P Value Not Exceeded 95% of Time) Leakage Current at Input Zero Reading Drift (Note 12) Scale Factor Temperature Coefficient (Note 12) System Electrical Specifications: ICL8052A/ICL71C03 V++ = +15V +5V -15V PARAMETER Zero Input Reading Ratiometric Error (Note 11) Linearity Over ...
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... System Electrical Specifications: ICL8052A/ICL71C03 V++ = +15V +5V -15V PARAMETER Differential Linearity (Difference between Worst Case Step of Adjacent Counts and Ideal Step) Rollover Error (Difference in Reading for Equal Positive & Negative Voltage Near Full Scale) Noise (Peak-To-Peak Value Not Exceeded 95% of Time) ...
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... C STRAY FIGURE 2C. PHASE III + DEINTEGRATE V (+1.000V) REF BUFFER REF STRAY FIGURE 2D. PHASE III - DEINTEGRATE FIGURE 2. ANALOG SECTION OF EITHER ICL8052A OR ICL8068A WITH ICL71C03 INT INT INTEGRATOR COMPARATOR - - ZERO A2 CROSSING + A3 DETECTOR + INT INT INTEGRATOR ...
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INTEGRATOR OUTPUT AZ PHASE I CLOCK INTERNAL LATCH BUSY OUTPUT NUMBER OF COUNTS TO ZERO CROSSING Zero-Crossing Flip-Flop Figure 4 shows the problem that the zero-crossing F/F is designated to solve. The ...
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RUN/HOLD (PIN 4) When high (or open) the A/D will free-run with equally spaced measurement cycles every 40,0002/4,002 clock pulses. If taken low, the converter will continue the full measurement cycle that it is doing and then hold this reading ...
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INTEGRATOR OUTPUT OVER-RANGE WHEN APPLICABLE UNDER-RANGE WHEN APPLICABLE DIGIT SCAN FOR OVER-RANGE STROBE DIGIT SCAN FOR OVER-RANGE Component Value Selection For optimum performance of the analog section, care must be taken in the selection of values for the integrator capacitor ...
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... The circuit recommended for doing this with the ICL8068A/ICL71C03 is shown in Figure 6. ICL8052A vs ICL8068A The ICL8052A offers significantly lower input leakage currents than the ICL8068A, and may be found preferable in systems with high input impedances. However, the ICL8068A has substantially lower noise voltage, and is the device of choice for systems where noise is a limiting factor, particularly in low signal level conditions ...
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... RBI input of Buffer Gain RB1 ----------------------------------- - R INT C INT REF V REF Resolution (4 NOTE: Comment on offset limitations above. Buffer gain does not improve ICL8052A noise performance adequately. digit conversion, use 12kHz clock Digit) or 12kHz (3 2 TABLE 1. SPECIFICATION VALUE 20 200 IN 100 10 RB2 + (See ...
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... OVER-RANGE 14 CLOCK IN 120kHz = 3 READINGS/SEC 1 NOTE: For 3 / digit, tie pin 2 low and change clock to 12kHz. 2 FIGURE 7. ICL8052A (8068A)/71C03A 4 POL +5V 5k 2.5k GATES ARE 7409 8052A/ 8068A FIGURE 8. ICL8052A-8068A/71C03A PLASMA DISPLAY CIRCUIT 150 150 ICL71C03 BUSY 28 (LSD ...
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... BUFF VOLTAGE OUT BUFF V REF -IN (IF USED 8068A PIN 2 COMPARATOR DEVICE PIN +5V SUPPLY BYPASS CAPACITOR(S) FIGURE 9. GROUNDING SEQUENCE EXTERNAL ANALOG SUPPLY REFERENCE BYPASS CAPACITORS (IF USED) +15V -15V PIN 5 ICL8052A/68A AN GND BOARD EDGE 1 /2 digit ANALOG SUPPLY RETURN DIGITAL SUPPLY RETURN ...
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... REF 7 REF. CAP REF. CAP 100k INPUT 10 INPUT 0 ANALOG GND CLOCK -15V 1 2 300 F 36k 3 ICL8052A 8068A 4 300k 5 -15V 10k 10 F ANALOG GND CD4054A BUSY ...
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... REF 7 8 REF. CAP REF. CAP 100k INPUT 10 INPUT 0 ANALOG GND CLOCK 1.0 F -15V 1 2 300 F 36k 3 ICL8052A 8068A 4 300k 5 -15V 10k 10 F ANALOG GND FIGURE 11 + CD4030 2 BUSY 28 CD4081 ...
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R 37.5k C 100pF FIGURE 12. CMOS OSCILLATOR 300pF FIGURE 14. GROSS OVERVOLTAGE PROTECTION CIRCUIT Interfacing with UARTs and Microprocessors Figure 15 shows a very simple interface between a free- running 8068A/8052A/71C03A and a UART. The five STROBE pulses start ...
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EPE POL FIGURE 15. SIMPLE ICL71C03/71C03A TO UART INTERFACE TRO RRI UART IM6402/3 EPE TBR ...
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FIGURE 17. IM6100 TO ICL71C03A/71C03A INTERFACE EN 1Y PA0 74C157 2Y PA1 PA2 SEL 1A PA3 MC6820 ...
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... ICL71C03 with ICL8052A/8068A Integrating A/D Converter Equations The ICL71C03 does not have an internal crystal or RC oscillator. It has a clock input only. Integration Period 10 000 t = -------------------- - 4-1/2 Digit CLOCK 1 000 t -------------------- - 3-1/2 Digit = CLOCK Integration Clock Period t = 1/f CLOCK CLOCK 60/50Hz Rejection Criterion Integer INT ...
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Dual-In-Line Plastic Packages (PDIP INDEX N/2 AREA -B- -A- D BASE PLANE -C- SEATING PLANE 0.010 (0.25 NOTES: 1. Controlling Dimensions: INCH. In case of conflict between ...
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Dual-In-Line Plastic Packages (PDIP INDEX N/2 AREA -B- -A- D BASE PLANE -C- SEATING PLANE 0.010 (0.25 NOTES: 1. Controlling Dimensions: INCH. In case of conflict between ...
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Ceramic Dual-In-Line Frit Seal Packages (CERDIP) -D- -A- E -B- bbb BASE Q PLANE -C- SEATING PLANE ccc ...