TC9462F_01 TOSHIBA [Toshiba Semiconductor], TC9462F_01 Datasheet - Page 3

• Manufacturer Part Number: TC9462F_01
• Description: Digital Servo Single Chip Processor
• Manufacturer: TOSHIBA [Toshiba Semiconductor]

Pin Function
Pin No.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
P2V
TESIO0
Symbol
MONIT
TEST0
UHSO
MBOV
HSSW
EMPH
DOUT
AOUT
SBOK
DATA
SBSY
SPCK
SPDA
COFS
LRCK
CLCK
SFSY
ZDET
HSO
PDO
BCK
V
V
V
V
IPF
DD
DD
SS
SS
REF
I/O
I/O
¾
¾
¾
¾
¾
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
Test mode terminal. Normally, keep at open.
Playback speed mode flag output terminal.
Subcode Q data emphasis flag output terminal.
Emphasis ON at “H” level and OFF at “L” level.
The output polarity can invert by command.
Channel clock output terminal. (44.1 kHz)
L-ch at “L” level and R-ch at “H” level. The output polarity can
invert by command.
Digital GND terminal.
Bit clock output terminal. (1.4112 MHz)
Audio data output terminal.
Digital data output terminal.
Buffer memory over signal output terminal.
Over at “H” level.
Correction flag output terminal.
At “H” level, AOUT output is made to correction impossibility
by C
Subcode Q data CRCC check adjusting result output
terminal. The adjusting result is OK at “H” level.
Subcode P~W data readout clock input/output terminal.
This terminal can select by command bit.
Digital power supply voltage terminal.
Digital GND terminal.
Subcode P~W data output terminal.
Play-back frame sync signal output terminal.
Subcode block sync signal output terminal.
Processor status signal readout clock output terminal.
Processor status signal output terminal.
Correction frame clock output terminal.
(7.35 kHz)
Internal signal (DSP internal flag and PLL clock) output
terminal. Selected by command.
This terminal output the text data with serial by command.
Digital power supply voltage terminal.
Test input/output terminal. Normally, keep at “L” level.
The terminal that inputted the clock for read of text data by
command.
PLL double reference voltage supply terminal.
This terminal is used to output PV
1 bit DA converter zero detect flag output terminal.
Phase difference signal output terminal of EFM signal and
PLCK signal.
2
correction processing.
UHSO
H
H
L
L
Functional Description
HSO
3
H
H
L
L
REF
or HiZ by command.
Playback Speed
Normal
2 times
4 times
¾
With pull-up resistor.
Schmitt input
2-state output.
(PV
3-state output.
(P2V
REF
REF
, HiZ)
, PV
Remarks
REF
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
2001-11-05
TC9462F
, V
SS
)