LM95235Q NSC [National Semiconductor], LM95235Q Datasheet - Page 14

• Manufacturer Part Number: LM95235Q
• Manufacturer: NSC [National Semiconductor]

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1.11 SERIAL INTERFACE RESET
In the event that the SMBus Master is RESET while the
LM95235 is transmitting on the SMBDAT line, the LM95235
must be returned to a known state in the communication pro-
tocol. This may be done in one of two ways:
1.
When SMBDAT is LOW, the LM95235 SMBus state
machine resets to the SMBus idle state if either SMBDAT
or SMBCLK are held low for more than 35 ms (t
Note that according to SMBus specification 2.0 all
devices are to timeout when either the SMBCLK or
SMBDAT lines are held low for 25 - 35 ms. Therefore, to
insure a timeout of all devices on the bus the SMBCLK
or SMBDAT lines must be held low for at least 35 ms.
TIMEOUT
).
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2.
1.12 ONE-SHOT CONVERSION
The One-Shot register is used to initiate a single conversion
and comparison cycle when the device is in standby mode,
after which the device returns to standby. This is not a data
register and it is the write operation that causes the one-shot
conversion. The data written to this address is irrelevant and
is not stored. A zero will always be read from this register.
When SMBDAT is HIGH, have the master initiate an
SMBus start. The LM95235 will respond properly to an
SMBus start condition at any point during the
communication. After the start the LM95235 will expect
an SMBus Address address byte.