LM95172EWG10A NSC [National Semiconductor], LM95172EWG10A Datasheet - Page 12

• Manufacturer Part Number: LM95172EWG10A
• Manufacturer: NSC [National Semiconductor]

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1.4 COMMUNICATING WITH THE LM95172EWG
The serial interface consists of three lines: CS (Chip Select),
SC (Serial Clock), and the bi-directional SI/O (Serial I/O) data
line. A high-to-low transition of the CS line initiates the com-
munication. The master (processor) always drives the chip
select and the clock. The first 16 clocks shift the temperature
data out of the LM95172EWG on the SI/O line (a temperature
read). Raising the CS at anytime during the communication
will terminate this read operation. Following this temperature
read, the SI/O line becomes an input and a command byte
can be written to the LM95172EWG. This command byte
FIGURE 11. Reading the Temperature Register followed by a read or write from another register (Control/Status, T
FIGURE 12. Reading the Temperature Register followed by repeated commands and Data Register accesses (Control/
FIGURE 10. Reading the Temperature Register
Status, T
T
LOW
HIGH
, or Identification register)
, T
LOW
, or Identification register)
12
contains a R/W bit and the address of the register to be com-
municated with next (see Section 1.7 Internal Register Struc-
ture). When writing, the data is latched in after every 8 bits.
The processor must write at least 8 bits in order to latch the
data. If CS is raised before the falling edge of the 8th com-
mand bit, no data will be latched into the command byte. If
CS is raised after the 8th bit, but before the 16th bit, of a write
to a 16-bit data register, only the most significant byte of the
data will be latched. This command-data-command-data se-
quence may be performed as many times as desired.
30076614
30076616
HIGH
30076615
,