BD9889FV_09 ROHM [Rohm], BD9889FV_09 Datasheet - Page 4

• Manufacturer Part Number: BD9889FV_09
• Description: Silicon Monolithic Integrated Circuit
• Manufacturer: ROHM [Rohm]

〇
１２．This IC is a monolithic IC which (as shown is Fig-1)has P
１. When designing the external circuit, including adequate margins for variation between external devices
２. The circuit functionality is guaranteed within of ambient temperature operation range as long as it is
３. Mounting failures, such as misdirection or miscounts, may harm the device.
４. A strong electromagnetic field may cause the IC to malfunction.
５. The GND pin should be the location within ±0.3V compared with the PGND pin.
６. BD9889FV incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD
７. Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become
８. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage
９. On operating Slow Start Control (SS is less than 2.2V), It does not operate Timer Latch.
１０.
１１.
NOTE FOR USE
and IC. Use adequate margins for steady state and transient characteristics.
within recommended operating range. The standard electrical characteristic values cannot be guaranteed
at other voltages in the operating ranges, however the variation will be small.
circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to
protect the IC or guarantee its operation of the thermal shutdown circuit is assumed.
significantly shortened. Moreover, the exact failure mode caused by short or open is not defined. Physical
countermeasures, such as a fuse, need to be considered when using a device beyond its maximum ratings.
is switching. Make sure to leave adequate margin for this IC variation.
state and the other state (0.8～1.6).
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can
result in mutual interference among circuits as well as operation faults and physical damage. Accordingly
you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than
the GND (P substrate) voltage to an input pin.
P-N junction is formed from this P layer of each pin. For example, the relation between each potential
is as follows,
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can
result in mutual interference among circuits as well as operation faults and physical damage. Accordingly
you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than
the GND (P substrate) voltage to an input pin.
This IC is a monolithic IC which (as shown is Fig-1) has P
A P-N junction is formed from this P layer of each pin. For example, the relation between each potential
is as follows,
By STB voltage, BD9889FV is changed to 2 states. Therefore, do not input STB pin voltage between one
The pin connected a connector need to connect to the resistor for electrical surge destruction.
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)
○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)
○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)
(PinA)
Ｎ
Fig-1 Simplified structure of a Bipolar IC
P
＋
Parasitic diode
(PinA)
Resistance
GND
P substrate
N
Parasitic diode
GND
P
P
Other adjacent components
＋
(PinB)
REV. A
Parasitic diode
Ｎ
(PinB)
C
Ｃ
Transistor (NPN)
B
P substrate
B
N
N
N
Ｂ
+
substrate and between the various pins. A
C
E
GND
+
GND
Ｅ
Ｃ
substrate and between the various pins.
Parasitic diode
E
N
GND
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