A6811ELW ALLEGRO [Allegro MicroSystems], A6811ELW Datasheet - Page 5

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A6811ELW

Manufacturer Part Number
A6811ELW
Description
DABiC-IV, 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER
Manufacturer
ALLEGRO [Allegro MicroSystems]
Datasheet

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Manufacturer
Quantity
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Part Number:
A6811ELW
Manufacturer:
ALLEGRO/雅丽高
Quantity:
20 000
Part Number:
A6811ELWT
Manufacturer:
ALLEGRO/雅丽高
Quantity:
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A. Data Active Time Before Clock Pulse
B. Data Active Time After Clock Pulse
C. Clock Pulse Width, t
D. Time Between Clock Activation and Strobe, t
E. Strobe Pulse Width, t
NOTE – Timing is representative of a 10 MHz clock. Signifi-
cantly higher speeds are attainable.
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
Serial Data present at the input is transferred to the shift
(Data Set-Up Time), t
(Data Hold Time), t
w(CH)
w(STH)
h(D)
su(D)
............................................... 25 ns
............................................... 50 ns
............................................. 50 ns
BLANKING
DATA OUT
BLANKING
STROBE
DATA IN
......................................... 25 ns
CLOCK
SERIAL
SERIAL
OUT
OUT
N
N
A
DATA
su(C)
50%
B
....... 100 ns
C
50%
LOW = ALL OUTPUTS ENABLED
D
50%
50%
t
p(CH-SQX)
t
en(BQ)
50%
HIGH = ALL OUTPUTS BLANKED (DISABLED)
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
drivers are disabled (OFF); the pnp active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.
E
t
p(STH-QL)
Information present at any register is transferred to the
When the BLANKING input is high, the output source
t
10%
p(STH-QH)
t
dis(BQ)
DATA
90%
LATCHED SOURCE DRIVER
t
r
DATA
10%
12-BIT SERIAL-INPUT,
90%
Dwg. WP-029
Dwg. WP-030
t
f
DATA
6811

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