A6833 ALLEGRO [Allegro MicroSystems], A6833 Datasheet - Page 4

• Manufacturer Part Number: A6833
• Description: DABiC-5 32-Bit Serial Input Latched Sink Drivers
• Manufacturer: ALLEGRO [Allegro MicroSystems]

NOTE: Timing is representative of a 10 MHz clock. Higher speeds
may be attainable; operation at high temperatures will reduce the
specified maximum clock frequency.
S
the logical 0 to logical 1 transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to the respective
latch when the STROBE is high (serial-to-parallel conversion). The
erial Data present at the input is transferred to the shift register on
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
OUT P UT E NAB LE
OUT P UT E NAB LE
Key
B
C
D
E
A
DAT A OUT
S T R OB E
DAT A IN
C LOC K
S E R IAL
S E R IAL
OUT
Data Active Time Before Clock Pulse (Data Set-Up Time)
Data Active Time After Clock Pulse (Data Hold Time)
Clock Pulse Width
Time Between Clock Activation and Strobe
Strobe Pulse Width
Timing Requirements and Specifications
OUT
N
N
A
(Logic Levels are V
DAT A
50%
B
Description
C
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Worcester, Massachusetts 01615-0036 [phone]
50%
HIG H = ALL OUT P UT S E NAB LE D
D
50%
50%
t
p(C H-S QX)
t
dis (B Q)
latches will continue to accept new data as long as the STROBE is
held high. Applications where the latches are bypassed (STROBE
tied high) will require that the OUTPUT ENABLE input be low
during serial data entry.
When the OUTPUT ENABLE input is low, the output sink drivers
are disabled (OFF). The information stored in the latches is not
affected by the OUTPUT ENABLE input. With the OUTPUT
ENABLE input high, the outputs are controlled by the state of their
respective latches.
DD
50%
LOW = ALL OUT P UT S B LANK E D (DIS AB LE D)
and Ground)
E
t
p(S T H-QL)
t
10%
p(S TH-QH)
t
en(B Q)
DAT A
90%
t
Symbol
DAT A
t
r
t
w(STH)
t
t
w(CH)
t
su(D)
su(C)
h(D)
10%
90%
Time (ns)
50%
100
25
25
50
50
t
DAT A
f
A6833
4