ADP1878-0.3-EVALZ AD [Analog Devices], ADP1878-0.3-EVALZ Datasheet - Page 4

• Manufacturer Part Number: ADP1878-0.3-EVALZ
• Description: Synchronous Buck Controller
• Manufacturer: AD [Analog Devices]

Parameter
OUTPUT DRIVER CHARACTERISTICS
PRECISION ENABLE THRESHOLD
COMP VOLTAGE
THERMAL SHUTDOWN
CURRENT LIMIT
OVERVOLTAGE AND POWER-
1
2
ADP1878/ADP1879
The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 59 and Figure 60), C
MOSFETs being Infineon BSC042N03MS G.
Not automatic test equipment (ATE) tested.
ADP1878ACPZ-0.6-R7/
ADP1878ACPZ-1.0-R7/
High-Side Driver
Low-Side Driver
Propagation Delays
SW Leakage Current
Integrated Rectifier
Logic High Level
Enable Hysteresis
COMP Clamp Low Voltage
COMP Clamp High Voltage
COMP Zero Current Threshold
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
Hiccup Current-Limit Timing
GOOD THRESHOLDS
FB Power-Good Threshold
FB Power-Good Hysteresis
FB Overvoltage Threshold
FB Overvoltage Hysteresis
PGOOD Low Voltage During Sink
PGOOD Leakage Current
ADP1879ACPZ-0.6-R7
On Time
Minimum On Time
Minimum Off Time
ADP1879ACPZ-1.0-R7
On Time
Minimum On Time
Minimum Off Time
Output Source Resistance
Output Sink Resistance
Rise Time
Fall Time
Output Source Resistance
Output Sink Resistance
Rise Time
Fall Time
DRVL Fall to DRVH Rise
DRVH Fall to DRVL Rise
Channel Impedance
2
2
2
2
2
2
Symbol
t
t
t
t
t
t
I
V
V
V
T
PGOOD
FB
FB
V
SWLEAK
r, DRVH
f, DRVH
r,DRVL
f,DRVL
tpdhDRVH
tpdhDRVL
TMSD
COMP(LOW)
COMP(HIGH)
COMP_ZCT
PGOOD
PGD
OV
Test Conditions/Comments
V
V
65% duty cycle (maximum)
V
V
45% duty cycle (maximum)
I
I
BST − SW = 4.4 V, C
BST − SW = 4.4 V, C
I
I
V
V
BST − SW = 4.4 V (see Figure 59)
BST − SW = 4.4 V (see Figure 60)
BST = 25 V, SW = 20 V, V
I
V
V
Tie EN pin to VREG to enable device
(2.75 V ≤ V
(2.75 V ≤ V
(2.75 V ≤ V
Rising temperature
COMP = 2.4 V
V
V
I
PGOOD = 5 V
SOURCE
SINK
SOURCE
SINK
SINK
PGOOD
IN
IN
IN
IN
REG
REG
IN
IN
FB
FB
= 5 V, V
= 20 V, V
= 5 V, V
= 20 V
= 2.9 V to 20 V, V
= 2.9 V to 20 V, V
rising during system power up
rising during overvoltage event, I
= 1.5 A, 100 ns, negative pulse (5 V to 0 V)
= 1.5 A, 100 ns, negative pulse (5 V to 0 V)
= 10 mA
= 5.0 V, C
= 5.0 V, C
= 1 mA
= 1.5 A, 100 ns, positive pulse (0 V to 5 V)
= 1.5 A, 100 ns, positive pulse (0 V to 5 V)
OUT
OUT
REG
REG
REG
OUT
Rev. A | Page 4 of 40
IN
IN
≤ 5.5 V)
≤ 5.5 V)
≤ 5.5 V)
= 2 V, T
= 2 V, T
= 0.8 V
= 4.3 nF (see Figure 60)
= 4.3 nF (see Figure 59)
IN
IN
REG
REG
J
J
= 4.3 nF (see Figure 59)
= 4.3 nF (see Figure 60)
= 25°C
= 25°C
= 2.75 V to 5.5 V
= 2.75 V to 5.5 V
REG
= 5 V
PGOOD
= 1 mA
GATE
= 4.3 nF, and the high- and low-side
Min
500
285
605
0.47
Typ
600
540
82
340
1.0
312
340
18
16
15.7
16
22.3
634
31
1.10
6
691
143
1
52
2.20
0.72
25
11
1.5
0.7
155
15
542
34
35
Data
Max
605
110
400
360
85
400
3
1
2.2
1
110
663
2.55
566
55
710
55
200
100
Sheet
Unit
kHz
ns
ns
ns
MHz
ns
ns
ns
Ω
Ω
ns
ns
Ω
Ω
ns
ns
ns
ns
μA
Ω
mV
mV
V
V
V
°C
°C
ms
mV
mV
mV
mV
mV
nA