ADP1876-EVALZ AD [Analog Devices], ADP1876-EVALZ Datasheet - Page 23

• Manufacturer Part Number: ADP1876-EVALZ
• Description: 600 kHz Dual Output Synchronous Buck
• Manufacturer: AD [Analog Devices]

3V TO 5.5V
Data Sheet
A resistor, shown as R
reduce overshoot and is generally between 2 Ω and 4 Ω. Adding
a resistor in series, typically between 2 Ω and 4 Ω, with the gate
driver also helps to reduce overshoot. If a gate resistor is added,
R
TYPICAL APPLICATIONS CIRCUIT
RISE
INPUT
1µF
is not needed.
VOUTLDO
(CHANNEL 1)
ADP1876
CIN = 150µF/20V, OS-CON, 20SEP150M, SANYO
L1, L2: 1.2µH, WURTH ELEKTRONIK, 744325120
M1, M3: BSC080N03LS
M2, M4: BSC030N03LS
Figure 32. Application Circuit with a Snubber
VDL
4.7µF
PGND1
73.2kΩ
BST1
ILIM1
10kΩ
1µF
SW1
DH1
DL1
330pF
1µF
RISE
R
R
22pF
RISE
ILIM1
in Figure 32 at the BST1 pin, helps to
44.2kΩ
1
2
3
4
5
6
7
8
V
IN
EN1
VIN
VINLDO
VOUTLDO
VCCO
VDL
AGND
NC
M1
M2
120pF
10kΩ
R
10pF
C
SNUB
SNUB
32
9
L
12.4kΩ
31
10
20kΩ
C
OUTx
30
11
V
OUT
ADP1876
TO
VIN
29
12
750kΩ
Figure 33. Typical Applications Circuit
CIN1, CIN2: 10µF/X7R/25V/1210 × 2, GRM32DR71E106KA12, MUR ATA
COUT
COUT
100nF
28
13
100nF
11
12
27
14
, COUT
, COUT
Rev. A | Page 23 of 24
26
15
21
22
: 330µF/6.3V/POSCAP × 2, 6TPF330M9L, SANYO
: 22µF/X5R/0805/6.3V × 3, GRM21BR60J226ME39, MUR ATA
25
16
PGND1
PGND2
SW1
SW2
DH1
DH2
DL1
DL2
PCB LAYOUT GUIDELINE
For additional information about PCB layout, see the
Application
Step-Down Regulators, Optimizing for Low Noise Design with
Dual Channel Switching Controllers.
AGND
0.1µF
0.1µF
24
23
22
21
20
19
18
17
PGND
CIN
22kΩ
Note, Printed Circuit Board Layout Guidelines for
2.1kΩ
2.1kΩ
22kΩ
V
IN
M1
M2
M3
M4
L2
L1
V
IN
CIN2
CIN1
= 10V TO 14V
COUT
COUT
21
11
COUT
COUT
ADP1876
22
12
V
5V@
13A
AN-1119
OUT1
V
1.8V@
13A
OUT2