LM2717-ADJ_08 NSC [National Semiconductor], LM2717-ADJ_08 Datasheet - Page 12

• Manufacturer Part Number: LM2717-ADJ_08
• Description: Dual Step-Down DC/DC Converter
• Manufacturer: NSC [National Semiconductor]

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Once the fp range is determined, R
using:
Where B is the desired gain in V/V at fp (fz1), gm is the
transconductance of the error amplifier, and R1 and R2 are
the feedback resistors as shown in Figure 3. A gain value
around 10dB (3.3v/v) is generally a good starting point.
Example: B = 3.3 v/v, gm=1350µmho, R1 = 20 KΩ, R2 = 59
KΩ:
Bandwidth will vary proportional to the value of Rc1. Next, Cc1
can be determined with the following equation:
Example: fpmin = 297 Hz, Rc1 = 20 KΩ:
The value of C
fpmin/max. A higher value will generally provide a more stable
loop, but too high a value will slow the transient response time.
The compensation network (Figure 3) will also introduce a low
frequency pole which will be close to 0Hz.
A second pole should also be placed at fz. This pole can be
created with a single capacitor Cc2 and a shorted Rc2 (see
Figure 3). The minimum value for this capacitor can be cal-
culated by:
Cc2 may not be necessary, however it does create a more
stable control loop. This is especially important with high load
currents.
Example: fz = 80 kHz, Rc1 = 20 KΩ:
c1
should be within the range determined by
c1
should be calculated
12
A second zero can also be added with a resistor in series with
Cc2. If used, this zero should be placed at fn, where the con-
trol to output gain rolls off at -40dB/dec. Generally, fn will be
well below the 0dB level and thus will have little effect on sta-
bility. Rc2 can be calculated with the following equation:
Note that the values calculated here give a good baseline for
stability and will work well with most applications. The values
in some cases may need to be adjusted some for optimum
stability or the values may need to be adjusted depending on
a particular applications bandwidth requirements.
LAYOUT CONSIDERATIONS
The LM2717-ADJ uses two separate ground connections,
PGND for the drivers and boost NMOS power device and
AGND for the sensitive analog control circuitry. The AGND
and PGND pins should be tied directly together at the pack-
age. The feedback and compensation networks should be
connected directly to a dedicated analog ground plane and
this ground plane must connect to the AGND pin. If no analog
ground plane is available then the ground connections of the
feedback and compensation networks must tie directly to the
AGND pin. Connecting these networks to the PGND can in-
ject noise into the system and effect performance.
The input bypass capacitor C
be placed close to the IC. This will reduce copper trace re-
sistance which effects input voltage ripple of the IC. For
additional input voltage filtering, a 0.1µF to 4.7µF bypass ca-
pacitors can be placed in parallel with C
pins to shunt any high frequency noise to ground. The output
capacitors, C
the IC. Any copper trace connections for the C
can increase the series resistance, which directly effects out-
put voltage ripple. The feedback network, resistors R
and R
the inductor to minimize copper trace connections that can
inject noise into the system. Trace connections made to the
inductors and schottky diodes should be minimized to reduce
power dissipation and increase overall efficiency. For more
detail on switching power supply layout considerations see
Application Note AN-1149: Layout Guidelines for Switching
Power Supplies.
FB2(4)
, should be kept close to the FB pin, and away from
FIGURE 3. Compensation Network
OUT1
and C
OUT2
, should also be placed close to
IN
, as shown in Figure 4, must
IN
, close to the V
OUTX
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capacitors
FB1(3)
IN