LT3756-1 LINER [Linear Technology], LT3756-1 Datasheet - Page 20

• Manufacturer Part Number: LT3756-1
• Description: 60VIN LED Controller with Internal PWM Generator
• Manufacturer: LINER [Linear Technology]

LT3761
applicaTions inFormaTion
Use the equation for Buck-Boost when choosing an in-
ductor value for SEPIC – if the SEPIC inductor is coupled,
then the equation’s result can be used as is. If the SEPIC
uses two uncoupled inductors, then each should have a
inductance double the result of the equation.
Table 6 provides some recommended inductor vendors.
Table 6. Recommended Inductor Manufacturers
MANUFACTURER
Coilcraft
Cooper-Coiltronics
Würth-Midcom
Vishay
Loop Compensation
The LT3761 uses an internal transconductance error
amplifier whose V
The external inductor, output capacitor and the compen-
sation resistor and capacitor determine the loop stability.
The inductor and output capacitor are chosen based on
performance, size and cost. The compensation resistor
and capacitor at V
response and stability. For typical LED applications, a 4.7nF
compensation capacitor at V
resistor should always be used to increase the slew rate
on the V
during fast transients on the input supply to the converter.
The DC-Coupling Capacitor Selection for SEPIC
LED Driver
The DC voltage rating of the DC-coupling capacitor C
connected between the primary and secondary inductors of
a SEPIC should be larger than the maximum input voltage:
C
the switch off-time, the current through C
approximately –I
voltage ripple causes current distortions on the primary
20
DC
V
CDC
has nearly a rectangular current waveform. During
C
> V
pin to maintain tighter regulation of LED current
IN(MAX)
LED
C
C
output compensates the control loop.
are selected to optimize control loop
flows during the on-time. The C
WEB
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C
is adequate, and a series
DC
is I
VIN
, while
DC
DC
and secondary inductors. The C
its voltage ripple. The power loss on the C
the LED driver efficiency. Therefore, the sufficient low ESR
ceramic capacitors should be selected. The X5R or X7R
ceramic capacitor is recommended for C
Board Layout
The high speed operation of the LT3761 demands care-
ful attention to board layout and component placement.
Figure 7 provides a suggested layout for the boost con-
verter. The exposed pad of the package is the only GND
terminal of the IC and is also important for its thermal
management. It is crucial to achieve a good electrical and
thermal contact between the exposed pad and the ground
plane of the board. To reduce electromagnetic interference
(EMI), it is important to minimize the area of the high dV/
dt switching node between the inductor, switch drain and
anode of the anode of the Schottky rectifier. Use a ground
plane under the switching node to eliminate interplane
coupling to sensitive signals.
Proper layout of the power paths with high di/dt is es-
sential to robust converter operation. The following high
di/dt loops of different topologies should be kept as tight
as possible to reduce inductive ringing:
1. In boost configuration, the high di/dt loop of each chan-
2. In buck mode configuration, the high di/dt loop of each
3. In buck-boost mode configuration, the high di/dt loop of
4. In SEPIC configuration, the high di/dt loop contains the
nel contains the output capacitor, the sensing resistor,
the power NMOS and the Schottky diode.
channel contains the input capacitor, the sensing resistor,
the power NMOS and the Schottky diode.
each channel contains the capacitor connecting between
V
and the Schottky diode.
power NMOS, sense resistor, output capacitor, Schottky
diode and the DC-coupling capacitor.
OUT
and GND, the sensing resistor, the power NMOS
DC
should be sized to limit
DC
DC
.
ESR reduces
3761f