LT3581 LINER [Linear Technology], LT3581 Datasheet - Page 16

• Manufacturer Part Number: LT3581
• Description: 3.3A Boost/Inverting DC/DC Converter with Fault Protection
• Manufacturer: LINER [Linear Technology]

LT3581
applicaTions inForMaTion
LAYOUT GUIDELINES FOR BOOST, SEPIC, AND DUAL
INDUCTOR INVERTING TOPOLOGIES
General Layout Guidelines
• To optimize thermal performance, solder the exposed
• A ground plane should be used under the switcher circuitry
• High speed switching path (see specific topology for
• The V
• Place the bypass capacitor for the V
• Place the bypass capacitor for the inductor as close as
• The load should connect directly to the positive and

Figure 8. Suggested Component Placement for Boost Topology
(MSOP Shown, DFN Similar, Not to Scale.) Pin 15 on DFN or
Pin 17 on MSOP Is the Exposed Pad Which Must Be Soldered
Directly to the Local Ground Plane for Adequate Thermal
Performance. Multiple Vias to Additional Ground Planes Will
Improve Thermal Performance
V
IN
ground pad of the LT3581 to the ground plane, with
multiple vias around the pad connecting to additional
ground planes.
to prevent interplane coupling and overall noise.
more information) must be kept as short as possible.
close to the LT3581 as possible, while being as far
away as practically possible from the switch node. The
ground for these components should be separated from
the switch current path.
possible to the LT3581.
possible to the inductor.
negative terminals of the output capacitor for best load
regulation.
–
+
A: RETURN C
COMBINE C
B: RETURN C
TO NOT COMBINE C
C
C
IN
IN
IN
OUT
, FB, and RT components should be placed as
GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT
AND C
OUT
L1
OUT1
AND C
A
GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
1
2
3
4
5
6
7
8
OUT1
GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
17
GND
D1
D2
16
15
14
13
12
11
10
9
B
IN
C
OUT1
C
pin as close as
R
OUT
GATE
M1
3581 F08
SYNC
SHDN
CLKOUT
–
+
V
OUT
Boost Topology Specific Layout Guidelines
• Keep length of loop (high speed switching path) gov-
SEPIC Topology Specific Layout Guidelines
• Keep length of loop (high speed switching path) gov-
Inverting Topology Specific Layout Guidelines
• Keep ground return path from the cathode of D1 (to
• Keep length of loop (high speed switching path) govern-
Figure 9. Suggested Component Placement for SEPIC Topology
(MSOP Shown, DFN Similar, Not to Scale.) Pin 15 on DFN or
Pin 17 on MSOP Is the Exposed Pad Which Must Be Soldered
Directly to the Local Ground Plane for Adequate Thermal
Performance. Multiple Vias to Additional Ground Planes Will
Improve Thermal Performance
erning switch, diode D1, output capacitor C
ground return as short as possible to minimize parasitic
inductive spikes at the switch node during switching.
erning switch, flying capacitor C1, diode D1, output
capacitor C
to minimize parasitic inductive spikes at the switch node
during switching.
chip) separated from output capacitor C
return path (to chip) in order to minimize switching
noise coupling into the output.
ing switch, flying capacitor C1, diode D1, and ground
return as short as possible to minimize parasitic induc-
tive spikes at the switch node during switching.
A: RETURN C
TO NOT COMBINE C
B: RETURN C
TO NOT COMBINE C
L1, L2: MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR IMPROVED
PERFORMANCE.
V
IN
–
+
IN
OUT
C
IN
AND L2 GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
GROUNDS DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
OUT
L1
IN
OUT
AND L2 GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
, and ground return as short as possible
A
1
2
3
4
5
6
7
8
L2
17
C1
D1
GND
16
15
14
13
12
11
10
9
B
C
OUT
3581 F09
OUT
OUT1
’s ground
SYNC
SHDN
CLKOUT
–
V
+
OUT
, and
3581f