LT3751 LINER [Linear Technology], LT3751 Datasheet - Page 16

• Manufacturer Part Number: LT3751
• Description: Capacitor Charger Controller with Regulation
• Manufacturer: LINER [Linear Technology]

applicaTions inForMaTion
LT3751
The total propagation delay, t
factor that affects efficiency and is the summation of gate
driver on-off propagation delays and the discharge time
associated with the secondary winding capacitance. There
are two effective methods to reduce the total propagation
delay. First, reduce the total capacitance on the secondary
winding, most notably the diode capacitance. Second,
reduce the total required NMOS gate charge. Figure 8
shows the effect of large secondary capacitance.
The energy stored in the secondary winding capacitance
is ½ • C
when the diode stops forward conduction. If the reflected
capacitance is greater than the total NMOS drain capaci-
tance, the drain of the NMOS power switch goes negative
and its intrinsic body diode conducts. It takes some time
for this energy to be dissipated and thus adds to the total
propagation delay.
Choosing Regulator Maximum I
The I
on the desired maximum output power instead of charge
time like that in a capacitor charger application.
Note that the LT3751 regulation scheme varies the peak
current based on the output load current. The maximum
I
load conditions where output power is maximized.
16
PK
V
DRAIN
I
I
I
SEC
PK
PRI
is only reached during charge mode or during heavy
PK
Figure 8. Effect of Secondary Winding Capacitance
= 2 •
SEC
parameter in regulation mode is calculated based
NO SEC.
CAPACITANCE
• V
P
Efficiency
OUT(AVG)
OUT
2
. This energy is reflected to the primary
SEC. DISCHARGE
•

 
V
TRANS
d
, is the second most dominant
1
PK
+
V
OUT
N

 
3751 F08
t
Transformer Design
The transformer’s primary inductance, L
by the desired V
parameters. Use the following equation to select L
The previous equation guarantees that the V
has enough time to sense the flyback waveform and trip
the DONE pin latch. Operating V
than that used to calculate L
condition and overcharge the output capacitor.
The L
tions. Note that if both I
for a given V
reached within the refresh clock period. This will result in
a lower than expected maximum output power. To prevent
this from occurring, maintain the condition in the follow-
ing equation.
The upper constraint on L
ing V
regulation occurs when operating the boundary-mode
frequency above 100kHz (refer to Operation section for
boundary-mode definition).
Figure 9 defines the maximum boundary-mode switching
frequency when operating at a desired output power level
and is normalized to L
ship of output power, boundary-mode frequency, I
primary inductance can be used as a guide throughout
the design process.
L
L
PRI
PRI
TRANS
PRI
=
<
equation is adequate for most regulator applica-
I
3µs • V
PK
and starting the design process over. The best
I
TRANS
PK
•



•N
V
OUT
OUT
TRANS
and V
38µs
1
and previously calculated N and I
PK
PRI
OUT
+
and N are increased significantly
/P
PRI
V
, the maximum I
OUT
PRI
N
OUT
can be reduced by increas-
could result in a runaway



(μH/Watt). The relation-
OUT
significantly higher
PRI
OUT
, is determined
PK
comparator
will not be
PK
PRI
, and
3751fc
:
PK