LT3519 LINER [Linear Technology], LT3519 Datasheet - Page 11

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LT3519

Manufacturer Part Number
LT3519
Description
LED Driver with Integrated Schottky Diode
Manufacturer
LINER [Linear Technology]
Datasheet

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APPLICATIONS INFORMATION
of capacitance value with increasing DC voltage bias, so
it may be necessary to choose a higher value capacitor
to get the required capacitance at the operation voltage.
Always check that the voltage rating of the capacitor is
suffi cient.
Table 2. Recommended Ceramic Capacitor Vendors
VENDOR
TDK
Kemet
Murata
Taiyo Yuden
Open LED Detection
The LT3519 provide an open-collector status pin,
OPENLED, that pulls low when the FB pin is within ~60mV
of its 1.22V regulated voltage. If the open LED clamp volt-
age is programmed correctly using the FB pin, then the FB
pin should never exceed 1.1V when LEDs are connected,
therefore, the only way for the FB pin to be within 60mV
of the 1.22V regulation voltage is for an open LED event
to have occurred.
Inrush Current
The LT3519 have a built-in Schottky diode for a boost
converter. When supply voltage is applied to V
voltage difference between V
current fl owing from input through the inductor and the
+
V
IN
Figure 4. High Frequency Path
PHONE
(516)535-2600
(408)986-0424
(814)237-1431
(408)573-4150
L1
SW
IN
and V
D1
OUT
WEB
www.tdk.com
www.kemet.com
www.murata.com
www.t-yuden.com
V
OUT
generates inrush
LOAD
3519 F04
IN
pin, the
Schottky diode to charge the output capacitor. The selection
of inductor and capacitor value should ensure the peak of
the inrush current to below 5A. In addition, the LT3519
turn-on should be delayed until the inrush current is less
than the maximum current limit.
Board Layout
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
To prevent electromagnetic interference (EMI) problems,
proper layout of high frequency switching paths (see
Figure 4) is essential. Minimize the length and area of all
traces connected to the switching node pin (SW). Keep the
sense voltage pins (ISP and ISN) away from the switching
node. The bypass capacitor on the V
should be placed as close as possible to the V
GND. Likewise, place C
not extensively route high impedance signals such as FB
and CTRL, as they may pick up switching noise. Figure 5
shows the recommended component placement.
L1
Figure 5. Suggested Layout
C
IN
GND
OPENLED
PWM
SHDN/UVLO
V
SW
ANODE
GND
V
IN
IN
OUT
CATHODE
next to the CATHODE pin. Do
CTRL
V
GND
GND
ISN
GND
ISP
REF
FB
IN
supply to the LT3519
C
OUT
LT3519
V
3519 F05
OUT
R
IN
S
pin and
11
3519f

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