STM8S207C6T3 STMICROELECTRONICS [STMicroelectronics], STM8S207C6T3 Datasheet - Page 79
STM8S207C6T3
Manufacturer Part Number
STM8S207C6T3
Description
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.STM8S207C6T3.pdf
(103 pages)
- Current page: 79 of 103
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STM8S207xx, STM8S208xx
Figure 37. SPI timing diagram - slave mode and CPHA = 0
Figure 38. SPI timing diagram - slave mode and CPHA = 1
1. Measurement points are done at CMOS levels: 0.3 V
OUT P UT
OUT P UT
NSS input
NSS input
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
I NPUT
I NPUT
MISO
MISO
MOSI
MOSI
t SU(NSS)
t a(SO)
t SU(NSS)
t a(SO)
t su(SI)
t w(SCKH)
t w(SCKL)
t w(SCKH)
t w(SCKL)
t su(SI)
MS B O UT
t v(SO)
M SB IN
M SB IN
t h(SI)
MS B O UT
t c(SCK)
t v(SO)
Doc ID 14733 Rev 9
t h(SI)
DD
t c(SCK)
and 0.7 V
BI T6 OUT
B I T1 IN
t h(SO)
DD.
B I T1 IN
BI T6 OUT
(1)
t h(SO)
LSB IN
t r(SCK)
t f(SCK)
LSB OUT
t r(SCK)
t f(SCK)
t h(NSS)
t h(NSS)
LSB IN
Electrical characteristics
LSB OUT
t dis(SO)
t dis(SO)
ai14134
ai14135
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