STM8S103XX STMICROELECTRONICS [STMicroelectronics], STM8S103XX Datasheet - Page 33

• Manufacturer Part Number: STM8S103XX
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STM8S103xx, STM8S105xx
Table 8.
Option byte no.
OPTBL
OPT3
OPT4
OPT5
OPT6
OPT7
Option byte description (continued)
LSI_EN: Low speed internal clock enable
IWDG_HW: Independent watchdog
WWDG_HW: Window watchdog activation
WWDG_HALT: Window watchdog reset on halt
EXTCLK: External clock selection
CKAWUSEL: Auto wake-up unit/clock
PRSC[1:0] AWU clock prescaler
HSECNT[7:0]: HSE crystal oscillator stabilization time
Reserved
Reserved
BL[7:0] Bootloader option byte
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for for AWU
00: Reserved
01: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
This configures the stabilisation time to 0, 16, 256, 4096 HSE cycles.
This option is checked by the boot ROM code after reset. Depending on
content of addresses 487Eh, 487Fh and 8000h (reset vector) the CPU
jumps to the bootloader or to the reset vector.
Refer to STM8S bootloader manual for more details.
Description
Option bytes
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