X9521 XICOR [Xicor Inc.], X9521 Datasheet - Page 7

• Manufacturer Part Number: X9521
• Description: Dual DCP, EEPROM Memory
• Manufacturer: XICOR [Xicor Inc.]

X9521 – Preliminary Information
and NVM. Therefore, the new “wiper position” setting is
recalled into the WCR after Vcc of the X9521 has been
powered down then powered back up
If WT is “0” then a DCP Volatile Write is performed. This
operation changes the DCP “wiper position” by writing
new data to the associated WCR only. The contents of the
associated NVM register remains unchanged. Therefore,
when Vcc to the device is powered down then back up,
the “wiper position” reverts to that last written to the DCP
using a nonvolatile write operation.
DCP Write Operation
A write to DCPx (x=1,2) can be performed using the three
byte command sequence shown in Figure 9.
In order to perform a write operation on a particular DCP ,
the Write Enable Latch (WEL) bit of the CONSTAT Regis-
ter must first be set (See “BL1, BL0: Block Lock protection
bits - (Nonvolatile)” on page 12.)
REV 1.1.9 1/30/03
† This bit has no effect when a Read operation is being performed.
WT
0
1
WRITE TYPE
†
S
T
A
R
T
Figure 8.
Select a Volatile Write operation to be performed
on the DCP pointed to by bits P1 and P0
Select a Nonvolatile Write operation to be per-
formed on the DCP pointed to by bits P1 and P0
1
I7
WT
0
SLAVE ADDRESS BYTE
I6
0
1
I5
0
Instruction Byte Format
0
1
I4
0
Description
1
I3
0
1
I2
0
Figure 9.
0
DCP SELECT
A
C
K
I1
P1
WT
I0
P0
0
INSTRUCTION BYTE
DCP Write Command Sequence
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0
0
0
The Slave Address Byte 10101110 specifies that a Write
to a DCP is to be conducted. An ACKNOWLEDGE is
returned by the X9521 after the Slave Address, if it has
been received correctly.
Next, an Instruction Byte is issued on SDA. Bits P1 and
P0 of the Instruction Byte determine which WCR is to be
written, while the WT bit determines if the Write is to be
volatile or nonvolatile. If the Instruction Byte format is
valid, another ACKNOWLEDGE is then returned by the
X9521.
Following the Instruction Byte, a Data Byte is issued to the
X9521 over SDA. The Data Byte contents is latched into
the WCR of the DCP on the first rising edge of the clock
signal, after the LSB of the Data Byte (D0) has been
issued on SDA (See Figure 25).
The Data Byte determines the “wiper position” (which
FET switch of the DCP resistive array is switched ON) of
the DCP . The maximum value for the Data Byte depends
upon which DCP is being addressed (see Table below).
Using a Data Byte larger than the values specified above
results in the “wiper terminal” being set to the highest tap
position. The “wiper position” does NOT roll-over to the
lowest tap position.
For DCP2 (256 Tap), the Data Byte maps one to one to
the “wiper position” of the DCP “wiper terminal”. There-
fore, the Data Byte 00001111 (15
ting the “wiper terminal” to tap position 15. Similarly, the
Data Byte 00011100 (28
0
P1- P0
0
0
1
1
P1 P0
0
1
0
1
DCPx
A
C
K
x=1
x=2
D7 D6 D5 D4 D3 D2 D1 D0
Characteristics subject to change without notice.
# Taps
DATA BYTE
10
100
256
) corresponds to setting the
Reserved
Reserved
10
) corresponds to set-
Refer to Appendix 1
Max. Data Byte
FFh
A
C
K
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T
O
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