STM8L101 STMICROELECTRONICS [STMicroelectronics], STM8L101 Datasheet - Page 11

• Manufacturer Part Number: STM8L101
• Description: 8-bit ultralow power microcontroller with up to 8 Kbytes Flash multifunction timers, comparators, USART, SPI, I2C
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STM8L101xx
3.5
3.6
3.7
3.8
3.9
Memory
The STM8L101xx devices have the following main features:
●
●
Error correction code is implemented on the EEPROM.
Low power modes
To minimize power consumption, the product features three low power modes:
●
●
●
Voltage regulators
The STM8L101xx embeds an internal voltage regulator for generating the 1.8 V power
supply for the core and peripherals.
This regulator has two different modes: main voltage regulator mode (MVR) and low power
voltage regulator mode (LPVR). When entering Halt or Active-halt modes, the system
automatically switches from the MVR to the LPVR in order to reduce current consumption.
Clock control
The STM8L101xx embeds a robust clock controller. It is used to distribute the system clock
to the core and the peripherals and to manage clock gating for low power modes. This
system clock is a 16-MHz High Speed Internal RC oscillator (HSI RC), followed by a
programmable prescaler.
In addition, a 38 kHz low speed internal RC oscillator is used by the independent watchdog
(IWDG) and Auto-wakeup unit (AWU).
Independent watchdog
The independent watchdog (IWDG) peripheral can be used to resolve processor
malfunctions due to hardware or software failures.
It is clocked by the 38 kHZ LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure.
1.5 Kbytes of RAM
The EEPROM is divided into two memory arrays (see the STM8L reference manual for
details on the memory mapping):
–
–
Wait mode: CPU clock stopped, selected peripherals at full clock speed.
Active-halt mode: CPU and peripheral clocks are stopped. The programmable wakeup
time is controlled by the AWU unit.
Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.
Wakeup is triggered by an external interrupt.
Up to 8 Kbytes of low-density embedded Flash program including up to 2 Kbytes
of data EEPROM. Data EEPROM and Flash program areas can be write protected
independently by using the memory access security mechanism (MASS).
64 option bytes (one block) of which 5 bytes are already used for the device.
Doc ID 15275 Rev 11
Product overview
11/81