LT3071EUFD LINER [Linear Technology], LT3071EUFD Datasheet - Page 12

• Manufacturer Part Number: LT3071EUFD
• Description: 5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator with Analog Margining
• Manufacturer: LINER [Linear Technology]

LT3071
pin Functions
SENSE (Pin 19): Kelvin Sense for OUT . The SENSE pin is
the inverting input to the error amplifier. Optimum regulation
is obtained when the SENSE pin is connected to the OUT
pins of the regulator. In critical applications, the resistance
(R
small voltage drops, creating a load regulation error at the
point of load. Connecting the SENSE pin at the load instead
of directly to OUT eliminates this voltage error. Figure 1
illustrates this Kelvin-Sense connection method. Note that
the voltage drop across the external PCB traces adds to the
dropout voltage of the regulator. The SENSE pin input bias
current depends on the selected output voltage. SENSE
pin input current varies from 50µA typically at V
to 300µA typically at V
I
sources a current typically equal to I
per amp of output current. Terminating this pin with a
resistor to GND produces a voltage proportional to I
For example, at I
With a 1k resistor to GND, this produces 2V. If I
unused, tie this pin to V
MARGA (Pin 22): Analog Margining: This pin margins the
output voltage over a continuous analog range of ±10%.
Tying this pin to GND adjusts output voltage by –10%.
Driving this pin to 1.2V adjusts output voltage by +10%. A
voltage source or a voltage output DAC is ideal for driving
this pin. If the MARGA function is not used, either float
this pin or terminate with a 1nF capacitor to GND.

MON
P
) of PCB traces between the regulator and the load cause
(Pin 21): Output Current Monitor. The I
OUT
= 5A, I
OUT
BIAS
= 1.8V.
.
MON
typically sources 2mA.
+
OUT
+
V
BIAS
/2500 or 400µA
V
IN
Figure 1. Kelvin Sense Connection
OUT
MON
= 0.8V
MON
pin
OUT
EN
IN
V
V
V
MARGA
VIOC
O0
O1
O2
is
.
LT3071
BIAS
GND
REF/BYP
PWRGD
V
lect. These three-state pins combine to select a nominal
output voltage from 0.8V to 1.8V in increments of 50mV.
Output voltage is limited to 1.8V maximum by an internal
override of V
threshold is less than 250mV referenced to GND and the
logic high threshold is greater than V
range between these two thresholds as set by a window
comparator defines the logic Hi-Z state. See Table 1 in the
Applications Information section that defines the V
and V
BIAS (Pin 27): Bias Supply. This pin supplies current to
the internal control circuitry and the output stage driving
the pass transistor. The LT3071 requires a minimum 2.2µF
bypass capacitor for stability and proper operation. To
ensure proper operation, the BIAS voltage must satisfy
the following conditions: 2.2V ≤ V
(1.25 • V
voltage is limited to 2.2V.
EN (Pin 28): Enable. This pin enables/disables the output
device only. The internal reference and all support functions
are active if V
EN low keeps the reference circuit active, but disables
the output pass transistor and puts the LT3071 into a low
power nap mode. Drive the EN pin with either a digital logic
port or an open-collector NPN or an open-drain NMOS
terminated with a pull-up resistor to V
resistor must be less than 35k to meet the V
of the EN pin. If unused, connect EN to BIAS.
SENSE
O0
I
OUT
MON
, V
O0
O1
settings versus V
R
R
OUT
P
P
and V
+ 1V). For V
3071 F01
O1
BIAS
O2
when V
LOAD
is above its UVLO threshold. Pulling
(Pins 23, 24, 25): Output Voltage Se-
O2
OUT
OUT
= high. The input logic low
≤ 0.95V, the minimum BIAS
.
BIAS
≤ 3.6V and V
BIAS
BIAS
– 250mV. The
. The pull-up
IH
condition
O2
BIAS
, V
3071f
O1
≥